Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Quadratic Programming Based Standard-cell Placement with New Additional Force

새로운 부가 힘을 사용한 Quadratic Programming 기반의 표준셀 배치

  • Published : 2002.06.01
Download PDF
⟨ Previous Next ⟩

Abstract

This paper deals with a standard cell placement which is based on a quadratic programming. This paper proposes a new additional force to reduce the cell overlap and to get a uniform distribution of cells. The additional force is not concerned with interconnections between cells, but it is determined by the density of a placement area. In this paper, we modelled that the new additional force is a force which is caused by the dummy fixed cell. And it is used for the global placement. Proposed placement method is compared with TimberWolf v7.0 and Itools vl.4. Proposed placer achieved 7.5% average reduction in wirelength in non timing driven mode, 5.0% average reduction in wlrelength in timing driven mode compared to TimberWolf v7.0. And we got a comparable result to Itools vl.4.

본 논문은 quadratic programming(QP) 기반의 표준셀 배치에 대하여 다룬다. 본 논문은 QP 기반의 배치에서 발생하는 셀겹침을 제거하고 균등한 배치를 얻기 위하여 새로운 모델의 부가 힘을 제안한다 부가 힘(additional force)이란, 셀 사이의 연결과는 관계없이 배치영역 내의 셀의 분포 밀도에 의해 받게되는 힘을 의미한다. 본 논문에서는 부가 힘을 가상 고정셀(dummy fixed cell)에 의해 발생되는 힘으로 모델화하여 그것을 이용한 개략배치 방법을 제안한다. 제안한 배치방법에 의한 최종 배치결과를 TimberWolf v7.0과 Itools vl.4와 비교하였다. 제안된 배치기는 시간지연을 고려하지 않은 경우, 배선거리에서 TimberWolf v7.0에 비하여 평균 7.5% 향상된 결과를 얻었다. 시간지연을 고려했을 경우, 배선거리에서 Timberwolf v7.0에 비하여 평균 5.0% 향상된 결과를 얻었다. 그리고 Itools vl.4에는 비교할만한 결과를 얻었다.

Keywords

References

  1. S. M. Areibi. 'Towards Optimal Circuit Layout Using Advanced Search Techniques,' PhD thesis, University of Waterloo, Ont. Canada, 1995
  2. K. Doll, F. M. Johannes, and K. J. Antreich, 'Iterative placement improvement by network flow methods,' IEEE Trans. CAD, Vol. 13, pp. 1190-1200, Oct, 1994 https://doi.org/10.1109/43.317462
  3. A. Dunlop and B. Kernighan, 'A Procedure for Placement of Standard-Cell VLSI Circuits,' IEEE Trans. CAD, Vol. CAD-4, No.1, pp. 92-98, Jan. 1985
  4. H. Eisenmann and F. M Johannes, 'Generic Global Placement and Floorplanning,' Proc. of ACM/IEEE DAC, pp. 269-274, 1998
  5. W. C. Elmore, 'The Transient Response of Damped Linear Network with Particular Regard to Wideband Amplifiers,' J. of Applied Physics, Vol. 19, pp. 55-63, 1948 https://doi.org/10.1063/1.1697872
  6. H. Etawil, S. Areibi, and A. Vannelli, 'Attractor-Repeller Approach for Global Placement,' Proc. of IEEE/ACM ICCAD, pp. 20-24, 1999 https://doi.org/10.1109/ICCAD.1999.810613
  7. C. M Fiduccia and R. M Mattheyses, 'A Liniear-Time Heuristic for Improving Network Partitions,' Proc. of ACM/IEEE DAC, pp. 175-181, 1982
  8. J. Frankie, 'Iterative and Adaptive Slack Allocation for Performance Driven Layout and FPGA Routing,' Proc. of ACM/IEEE DAC, 1992, pp. 536-542 https://doi.org/10.1109/DAC.1992.227746
  9. G. H. Golub and C. F. Van Loan, Matrix Computations, 3ed, Baltimore: Johns Hopkins University, 1996
  10. D. J. Huang and A. B. Kahng, 'Partitioning-Based Standard-Cell Global Placement with an Exact Objective,' Proc. ACM/IEEE ISPD, pp. 18-25, April 1997 https://doi.org/10.1145/267665.267674
  11. B. W. Kernighan and S. Lin. 'An Efficient Heuristic Procedure for Partitioning Graphs,' Bell Syst, Tech. J., 49(2):291-307, 1970 https://doi.org/10.1002/j.1538-7305.1970.tb01770.x
  12. J. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich. 'GORDIAN: VLSI Placement by Quadratic Programming and Slicing optimization,' IEEE Trans. CAD, Vol. CAD-10, No.3, pp. 356-365, 1991 https://doi.org/10.1109/43.67789
  13. K. Koziminski, 'Benchmarks for Layout Synthesis - Evolution and Current Status,' Proc. of ACM/IEEE DAC, pp 265-270, 1991 https://doi.org/10.1145/127601.127678
  14. T. Ohtsuki, Layout Design And Veryfication, North Holand, 1985
  15. B. M. Riess and G. G. Ettelt. 'SPEED: Fast and Efficient Timing Driven Placement,' Proc. of the IEEE International Symposium on Circuits and Systems, pp. 377-380, 1995 https://doi.org/10.1109/ISCAS.1995.521529
  16. J. Rubinstein, J. P. Penfield and H Horowitz, 'Signal Delay in RC-Tree Networks,' IEEE Trans. on CAD, Vol. CAD-2, No.3, pp. 202-211, 1983
  17. G. Sigl, K. Doll, and F. M. Johannes. 'An alytical Placement: A Linear or a Quadratic Objective Function?' Proc. of ACM/IEEE DAC, pp. 427-432, 1991
  18. P. R. Suaris and G. Kedem, 'An Algorithm for Quadrisection and Its Application to Standard Cell Placement', IEEE trans. on CAS, Vol. 35, No.3, pp. 294 - 303, 1988 https://doi.org/10.1109/31.1742
  19. W.-J. Sun and C. Sechen, 'Efficient and effective placement for very large circuits', IEEE Trans. CAD, Vol. 14, No.3, pp. 349-359, 1995 https://doi.org/10.1109/43.365125
  20. D. Sylvester and K Keutzer, 'Rethinking Deep-Submicron Circuit Design', IEEE Computer, Vol. 32, No. 11, pp. 25-33, November 1999 https://doi.org/10.1109/2.803637