실리콘 선택적 결정 성장 공정을 이용한 Elevated Source/drain물 갖는 NMOSFETs 소자의 특성 연구

A Study on the Device Characteristics of NMOSFETs Having Elevated Source/drain Made by Selective Epitaxial Growth(SEG) of Silicon

  • 발행 : 2002.03.01

초록

Deep submicron NMOSFETs with elevated source/drain can be fabricated using self-aligned selective epitaxial growth(SEG) of silicon for enhanced device characteristics with shallow junction compared to conventional MOSFETs. Shallow junctions, especially with the heartily-doped S/D residing in the elevated layer, give hotter immunity to Yt roll off, drain-induced-barrier-lowering (DIBL), subthreshold swing (SS), punch-through, and hot carrier effects. In this paper, the characteristics of both deep submicron elevated source/drain NMOSFETs and conventional NMOSFETs were investigated by using TSUPREM-4 and MEDICI simulators, and then the results were compared. It was observed from the simulation results that deep submicron elevated S/D NMOSFETs having shallower junction depth resulted in reduced short channel effects, such as DIBL, SS, and hot carrier effects than conventional NMOSFETs. The saturation current, Idsat, of the elevated S/D NMOSFETs was higher than conventional NMOSFETs with identical device dimensions due to smaller sheet resistance in source/drain regions. However, the gate-to-drain capacitance increased in the elevated S/D MOSFETs compared with the conventional NMOSFETs because of increasing overlap area. Therefore, it is concluded that elevated S/D MOSFETs may result in better device characteristics including current drivability than conventional NMOSFETs, but there exists trade-off between device characteristics and fate-to-drain capacitance.

키워드

참고문헌

  1. T. Ohguro, S. Nakamura, M. Saito, M. Ono, H. Harakawa, E. Morifuji, T. Yoshitomi, T. Morimoto, H. S. Momose, Y. Katsumata, H. Iwai, 'Ultra-shallow junction and salicide techniques for advanced CMOSFET devices', Proc. Electrochem. Soc., vol. 97, p. 275, 1997
  2. The National Technology Roadmap for Semiconductors. San Jose, CA: Semiconductor Ind. Assoc., 1999
  3. S. Thompson, P. Packan, M. Bohr, 'MOSFET scaling: Transistor challenges for the 21st century', Intel Technol. J., p. 1, 1998
  4. Y. Taur, E. J. Nowak, 'CMOSFET devices below $0.1{\mu}m$: How high will performance go?', in IEDM Tech. Dig., 1997, p. 215
  5. N. Miura, Y. Abe, K. Sugihara, T. Oishi, T. Furukawa, T. Nakahata, K. Shiozawa, S. Maruno, Y. Tokuda, 'Junction capacitance reduction due to self-aligned pocket implantation in elevated source/drain NMOSFETs', IEEE Trans. Electron Devices, vol. 48, pp. 1969-1974, 2001 https://doi.org/10.1109/16.944184
  6. J. J. Sun, R. F. Bartholomew, K. Bellur, A. Srivastava, C. M. Osburn, N. A. Masnari, 'The effect of the elevated source/drain doping profile on performance and reliability of deep submicron MOSFET's', IEEE Trans. Electron Devices, vol. 44, pp. 1491-1498, 1997 https://doi.org/10.1109/16.622606
  7. K. Sugihara, Y. Abe, T. Oishi, N. Miura, Y. Tokuda, 'Short channel characteristics of quasi-single-drain MOSFETs', IEEE Electron Device Letters, vol. 22, 2001, pp. 351-353 https://doi.org/10.1109/55.930688
  8. J. J. Sun, C. M. Osburn, 'Impact of epi facets on deep submicron elevated source/drain MOSFET characteristics', IEEE Transactions on Electron Devices, vol. 45, pp. 1377-1380, 1998 https://doi.org/10.1109/16.678583
  9. Y. Taur, T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1988