전자공학회논문지CI (Journal of the Institute of Electronics Engineers of Korea CI)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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휴대 단말기용 32 비트 RISC 코어 구현

Implementation of a 32-Bit RISC Core for Portable Terminals

  • 발행 : 2001.11.25
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문은 셀룰러 폰, PDA, 노트북 등과 같은 휴대 단말 시스템에서 내장형으로 사용될 수 있는 32비트 RISC 코어 구현에 대해서 기술하였다. RISC 코어는 ARM$\circled$V4 명령어 셋을 따르며 전형적인 5단 파이프 라인으로 동작한다. 또한 보다 향상된 코드 밀도를 위해 Thumb 코드를 지원하고, 파이프라인 레지스터의 동적 전력 관리 기법을 사용한다. RTL 수준에서 VHDL로 모델링된 코어는 ADS의 ARMulator와 비교 검증되었으며 평균 CPI는 1.44이다. 검증이 완료된 코어는 $0.6{\mu}m$ CMOS 1-poly 3-metal 셀라이브러리를 사용하여 합성 및 레이아웃되었으며 크기는 약 41,000 게이트이고, 예상 동작주파수는 45 MHz이다.

This paper describes implementation of an embedded 32-Bit RISC core for portable communication/information equipment, such as cellular phones, PDA(Personal Digital Assistants), notebook, etc. The RISC core implements the ARM$\circled$V 4 instruction set, operates with typical 5-stage pipeline. It supports Thumb code to improve the code density, and uses the dynamic power management method of pipeline registers. It was modeled and simulated in RTL level using VHDL, and verified with ARMulator of ADS (Arm Developer Suite) and had average CPI of 1.44. The core is synthesized automatically using the cell library based on $0.6{\mu}m$ CMOS 1-poly 3-metal CMOS technology. It consists of about 41,000 gates and the clock frequency is expected to be above 45 MHz.

키워드

참고문헌

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