참고문헌
- Proc. of the 30th DAC VIPER : An Efficient Vigorously Sensitizable Path Extractor H. Chang;J. A. Abraham
- Proc. of the 28th DAC Incremental Techniques for the Identification of Statically Sensitizable Critical Paths Y. C.Ju;R. A. Saleh
- IEEE Transactions on VLSI systems v.4 no.3 Efficient Logic-Level Timing Analysis Using Constraint-Guided Critical Path Search C. Oh.;M. R. Mercer
- IEEE Transactions on Computer Aided Design of Intergrated Circuits and Systems v.14 no.8 Functional Timing Analysis Using ATPG P. Ashar;S. Malik
- Proc. of the 30th DAC A Polynomial-Timing Heuristic Approach to Approximate a Solution to the False Path Problem S.T. Hung;T. M. Parng;J. M. Shyu
- IEEE Int. Conf. Computer-Aided Design A New Approach to Solving False Path Problem in Timing Analysis S. T. Hung;T. M. Parng;J. M.Shyu
- IEEE Transactions on Circuits and Systems-Fundamental Theory and Applications v.43 no.5 A Polynomial-Time Heuristic Approach to Solving the False Path Problem S. T. Huang;T. M. Parng;J. M. Shyu
- IEEE Transactions on Computers v.C-35 no.8 Graph-Based Algorithms for Boolean Function Manipulation R. E. Bryant
- Proc. of the 30th DAC Algebraic Decision Diagrams and Their Applicatiions R. I. Bahar;E. A. Frohm;C. M. Gaona;G. D. Hachtel;E. Macii;A. Pardo;F.Somenzi
- IEEE International Symposium on Circuits and Systems ISCAS-85 Benchmarks, Special Session: Recent Algorithms for Gate Level ATPG with Fault Simulation and Their Performance Assessment
- Proc. of the DAC Hierarchical Functional Timing Analysis Yuji Kukimoto;Robert K. Brayton
- IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems v.15 no.2 Timing Analysis Speed-up Using a Hierarchical and a Multimode Approach Y. Blaquiere;M. Dagenais;Y. Savaria
- Proc. of the ICCCAD Path Sensitization in Critical Path Problem H. C. Chen;D. H. C. Du
- Computer Digital Logic in a Time Based Table Driven Environment Part 1; Design Verification S. A. Szygenda;E. W. Thomson