Timing Analysis by Concurrent Event Propagation

병렬 사건전파 방식에 의한 타이밍 분석

  • 한창호 (인하대 전자계산공학과)
  • Published : 1999.10.01

Abstract

This paper proposes concurrent event propagation technique for timing analysis. The technique makes it possible to find several input vectors and sensitizable paths at the same time. The concurrent event propagation technique is based on the event driven simulation and the timing analysis technique with boolean equations. The technique propagates as many events as possible at the same time while preventing propagation of boolean terms which do not sensitize paths. Since events do not propagate through false paths, the longest path which successfully propagates events to one of the primary outputs is one of the longest sensitizable paths. The technique can speed up timing analysis by unifying path sensitization and maximum delay calculation.

Keywords

References

  1. Proc. of the 30th DAC VIPER : An Efficient Vigorously Sensitizable Path Extractor H. Chang;J. A. Abraham
  2. Proc. of the 28th DAC Incremental Techniques for the Identification of Statically Sensitizable Critical Paths Y. C.Ju;R. A. Saleh
  3. IEEE Transactions on VLSI systems v.4 no.3 Efficient Logic-Level Timing Analysis Using Constraint-Guided Critical Path Search C. Oh.;M. R. Mercer
  4. IEEE Transactions on Computer Aided Design of Intergrated Circuits and Systems v.14 no.8 Functional Timing Analysis Using ATPG P. Ashar;S. Malik
  5. Proc. of the 30th DAC A Polynomial-Timing Heuristic Approach to Approximate a Solution to the False Path Problem S.T. Hung;T. M. Parng;J. M. Shyu
  6. IEEE Int. Conf. Computer-Aided Design A New Approach to Solving False Path Problem in Timing Analysis S. T. Hung;T. M. Parng;J. M.Shyu
  7. IEEE Transactions on Circuits and Systems-Fundamental Theory and Applications v.43 no.5 A Polynomial-Time Heuristic Approach to Solving the False Path Problem S. T. Huang;T. M. Parng;J. M. Shyu
  8. IEEE Transactions on Computers v.C-35 no.8 Graph-Based Algorithms for Boolean Function Manipulation R. E. Bryant
  9. Proc. of the 30th DAC Algebraic Decision Diagrams and Their Applicatiions R. I. Bahar;E. A. Frohm;C. M. Gaona;G. D. Hachtel;E. Macii;A. Pardo;F.Somenzi
  10. IEEE International Symposium on Circuits and Systems ISCAS-85 Benchmarks, Special Session: Recent Algorithms for Gate Level ATPG with Fault Simulation and Their Performance Assessment
  11. Proc. of the DAC Hierarchical Functional Timing Analysis Yuji Kukimoto;Robert K. Brayton
  12. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems v.15 no.2 Timing Analysis Speed-up Using a Hierarchical and a Multimode Approach Y. Blaquiere;M. Dagenais;Y. Savaria
  13. Proc. of the ICCCAD Path Sensitization in Critical Path Problem H. C. Chen;D. H. C. Du
  14. Computer Digital Logic in a Time Based Table Driven Environment Part 1; Design Verification S. A. Szygenda;E. W. Thomson