전자공학회논문지C (Journal of the Korean Institute of Telematics and Electronics C)
- 제34C권8호
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- Pages.22-38
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- 1997
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- 1226-5853(pISSN)
새로운 수리형태학 필터 VLSI 구조 설계
Design of a new VLSI architecture for morphological filters
초록
This paper proposes a new VLSI architecture for morphological filters and presents its chip design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architecture by using a feedback loop path to reuse partial results and a decoder/encoder pair to detect maximum/minimum values. In addition, the proposed architecture requires one common architecture for both diltion and erosion and fewer number of operations. Moreover, it can be easily extended for larger size morphologica operations. We developed VHDL (VHSIC hardware description language) models, performed logic synthesis using the SYNOPSYS CAD tool. We used the SOG (sea-of-gate) cell library and implemented the actual chip. The total number of gates is only 2,667 and the clock frequency is 30 MHz that meets real-time image processing requirements.
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