전자공학회논문지C (Journal of the Korean Institute of Telematics and Electronics C)
- 제34C권8호
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- Pages.8-21
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- 1997
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- 1226-5853(pISSN)
초 고집적 메모리의 효율적인 테스트를 위한 BIST 회로와 BICS의 설계
A design of BIST circuit and BICS for efficient ULSI memory testing
초록
In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in MOS FETs included in typical memory cell of VLSI SRAM and analyze behavior of memory by using PSPICE simulation. Using conventional fault models and this behavioral analysis, we propose linear testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ (quiescent power supply current) testing simultaneously to improve functionality and reliability of memory. Finally, we implement BIST (built-in self tsst) circuit and BICS(built-in current sensor), which are embedded on memory chip, to carry out functional testing efficiently and to detect various defects at high-speed respectively.
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