전자공학회논문지A (Journal of the Korean Institute of Telematics and Electronics A)
- 제29A권2호
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- Pages.77-79
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- 1992
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- 1016-135X(pISSN)
자기정렬 이중 리쎄스 공정에 의한 전력 MESFET 소자의 제작
Power MESFETs Fabricated using a Self-Aligned and Double Recessed Gate Process
초록
We propose a self-aligned and double recessed technique for GaAs power MESFETs application. The gate length and the wide recess width are defined by a selective removal of the SiN layer using reactive ion etching(RIE) while the depth of the channel is defined by chemical etching of GaAs layers. The threshold voltages and the saturation drain voltage could be sucessfully controlled using this technique. The lateral-etched distance increases with the dry etching time and the source-drain breakdown voltage of MESFET increases up to about 30V at a pinch-off condition. The electrical characteristics of a MESFET with a gate length of 2 x10S0-6Tm and a source-gate spacing of 33 x10S0-6Tm show maximum transconductance of 120 mS/mm and saturation drain current density of 170-190mA/mm at a gate voltage of 0.8V.
키워드