전자공학회논문지A (Journal of the Korean Institute of Telematics and Electronics A)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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논리 회로의 기술 매핑 시스템 설계

Design of a Technology Mapping System for Logic Circuits

  • 김태선 (서강대학교 전자공학과) ;
  • 황선영 (서강대학교 전자공학과)
  • 발행 : 1992.02.01
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초록

This paper presents an efficient method of mapping Boolean equations to a set of library gates. The proposed system performs technology mapping by graph covering. To select optimal area cover, a new cost function and local area optimization are proposed. Experimental results show that the proposed algorithm produces effective mapping using given library.

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