A New Minimizing Algorithm for Design the PLA of Multiple Output Combinational Circuits

다출력조합회로의 PLA설계를 위한 간소화 알고리즘

In the design of PLA's of VLSI, as the number of subsets of functions from which common preme implicants must be determined increases, the execution time increases by a factor of O(2\ulcorner. When the number of functions N is a large number, this poses a serious problem in minumization of multiple-output logic functions. In this paper a new algorithm that minimizes multiple-output logic functions is proposed. The algorithm requires less number of Fortran statements, less execution time, and less memory area than existing methods. The bases of this algorithm are explained and verified, and the sequential operation for preparation of the program is discussed.