Proceedings of the Korean Institute of Information and Commucation Sciences Conference (한국정보통신학회:학술대회논문집)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Design of an eFuse OTP Memory of 8 Bits for PMICs and its Measurement

PMIC용 8비트 eFuse OTP Memory 설계 및 측정

  • Park, Young-Bae (Department of Electronic Eng., Changwon National University) ;
  • Choi, In-Hwa (Department of Electronic Eng., Changwon National University) ;
  • Lee, Dong-Hoon (Department of Electronic Eng., Changwon National University) ;
  • Jin, Liyan (Department of Electronic Eng., Changwon National University) ;
  • Jang, Ji-Hye (Department of Electronic Eng., Changwon National University) ;
  • Ha, Pan-Bong (Department of Electronic Eng., Changwon National University) ;
  • Kim, Young-Hee (Department of Electronic Eng., Changwon National University)
  • Published : 2012.05.26
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Abstract

In this paper, we design an 8-bit eSuse OTP (one-time programmable) memory based on a $0.35{\mu}m$ BCD process using differential paired eFuse cells which can sense BL data without a reference voltage and also have smaller sensing resistances of programmed eFuse links. The channel widths of a program transistor of the differential eFuse OTP cell are splitted into $45{\mu}m$ and $120{\mu}m$. Also, we implement a sensing margin test circuit with variable pull-up loads in consideration of variations of the programmed eFuse resistances. It is confirmed by measurement results that the designed 8-bit eFuse OTP memory IP gives a better yield when the channel width is $120{\mu}m$.

본 논문에서는 프로그램 된 eFuse 링크의 센싱 저항이 작으면서 기준 전압없이 BL 데이터를 센싱가능한 differential paired eFuse 셀을 사용하여 BCD 공정 기반의 8비트 eFuse OTP를 설계하였다. Differential eFuse OTP 셀의 프로그램 트랜지스터의 채널 폭은 $45{\mu}m$과 $120{\mu}m$으로 split하였다. 그리고 프로그램된 eFuse 저항의 변동을 고려한 variable pull-up load를 갖는 센싱 마진 테스터(sensing margin test) 회로를 구현하였다. $0.35{\mu}m$ BCD 공정을 이용하여 제작된 8bit eFuse OTP IP를 측정한 결과 프로그램 트랜지스터의 채널 폭이 $120{\mu}m$인 OTP IP의 수율이 $45{\mu}m$인 OTP IP보다 양호한 것으로 나타났다.

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