Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2008.06a
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- Pages.1069-1070
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- 2008
A High Efficient, Two-Stage Interleaved Synchronous Buck CMOS DC-DC Converter
고효율 2단 인터리브 동기정류형 벅 컨버터
- Park, Jong-Ha (Department of Electronics, Electrical, Control, and Instrumentation Engineering Hanyang University) ;
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Kim, Hoon
(Department of Electronics, Electrical, Control, and Instrumentation Engineering Hanyang University) ;
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Kim, Hee-Jun
(Department of Electronics, Electrical, Control, and Instrumentation Engineering Hanyang University)
- Published : 2008.06.18
Abstract
This paper presents a high efficient two-stage interleaved synchronous buck CMOS DC-DC converter. The proposed circuit has a fixed duty cycle as 0.5 by an added buck converter. And it causes the best ripple cancelation of the output current ripple. The proposed circuit was simulated by HSPICE with a standard CMOS
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