A High Efficient, Two-Stage Interleaved Synchronous Buck CMOS DC-DC Converter

고효율 2단 인터리브 동기정류형 벅 컨버터

  • Park, Jong-Ha (Department of Electronics, Electrical, Control, and Instrumentation Engineering Hanyang University) ;
  • Kim, Hoon (Department of Electronics, Electrical, Control, and Instrumentation Engineering Hanyang University) ;
  • Kim, Hee-Jun (Department of Electronics, Electrical, Control, and Instrumentation Engineering Hanyang University)
  • 박종하 (한양대학교 전기전자제어계측공학과) ;
  • 김훈 (한양대학교 전기전자제어계측공학과) ;
  • 김희준 (한양대학교 전기전자제어계측공학과)
  • Published : 2008.06.18

Abstract

This paper presents a high efficient two-stage interleaved synchronous buck CMOS DC-DC converter. The proposed circuit has a fixed duty cycle as 0.5 by an added buck converter. And it causes the best ripple cancelation of the output current ripple. The proposed circuit was simulated by HSPICE with a standard CMOS $0.35{\mu}m$ process parameter.

Keywords