Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Numerical Analysis of the Relation of the Bandwidth and Locking Speed of the Analog DLL in Time Domain

시간 영역에서 아날로그 DLL의 Bandwidth 와 Locking Speed 관계의 수식적 분석

  • Ryu, Kyung-Ho (School of Electrical and Electric Engineering at Yonsei University) ;
  • Jung, Seong-Ook (School of Electrical and Electric Engineering at Yonsei University)
  • 류경호 (연세대학교 전기전자공학부) ;
  • 정성욱 (연세대학교 전기전자공학부)
  • Published : 2008.06.18
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Abstract

Locking time of the DLL is the important design issue in case of clock gating for low power system. For precise analysis of the locking speed of the DLL, this paper analyzes the locking process of the DLL in time domain. Analysis result shows that the value of the DLL bandwidth over reference frequency should be limited to below 1 ($i.e.w_n/F_{REF}<1$) for the stable operation and relation between bandwidth and lock time is expressed by log function.

Keywords