Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Dual-Precharge Conditional-Discharge Flip-Flop for High-Speed Low-Power SoC

고 성능 저 전력 SoC를 위한 Dual-Precharge Conditional-Discharge Flip-Flop

  • Park, Yoon-Suk (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kang, Sung-Chan (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kong, Bai-Sun (School of Information and Communication Engineering, Sungkyunkwan University)
  • 박윤석 (성균관대학교 정보통신공학부) ;
  • 강성찬 (성균관대학교 정보통신공학부) ;
  • 공배선 (성균관대학교 정보통신공학부)
  • Published : 2008.06.18
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Abstract

This paper presents a low-power and high-speed pulsed flip-flop based on dual-precharging and conditional discharging. The dual-precharging operation minimizes the parasitic capacitance of each precharge node, resulting in high-speed operation. The conditional-discharging operation minimizes the redundant transitions of precharge nodes, resulting in low-power operation. Linear feedback shift register (LFSR) designed in a $0.18{\mu}m$ CMOS technology using the proposed flip-flop achieves 32% power reduction as compared to conventional design.

Keywords