Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of a 10Gbps CMOS Clock and Data Recovery Circuit

10Gbps CMOS 클럭/데이터 복원 회로 설계

  • Cha, Chung-Hyeon (Dept. of Electronic Engineering University of Incheon) ;
  • Sim, Sang-Mi (Dept. of Electronic Engineering University of Incheon) ;
  • Park, Jong-Tae (Dept. of Electronic Engineering University of Incheon) ;
  • Yu, Chong-Gun (Dept. of Electronic Engineering University of Incheon)
  • Published : 2008.06.18
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Abstract

In this paper, a 10Gbps clock and data recovery circuit is designed in $0.18{\mu}m$ CMOS technology. The circuit incorporates a multiphase LC oscillator, a quarter-rate Bang-Bang phase detector, a charge pump and a second order loop filter. The simulation results show that the designed circuit has a peak-to-peak clock jitter of 4.2ps and a peak-to-peak recovered data jitter of 8ps while consuming about 80mW from a 1.8V supply.

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