DRAM bus system을 위한 analog calibration 적용 Pre-emphasis Transmitter

  • 박정준 (한양대학교 전자통신컴퓨터공학부) ;
  • 차수호 (한양대학교 전자통신컴퓨터공학부) ;
  • 유창식 (한양대학교 전자통신컴퓨터공학부) ;
  • 기중식 (하이닉스반도체)
  • 발행 : 2006.06.21

초록

A Pre-emphasis transmitter for DRAM bus system has achieved 3.2Gbps/pin operation at 1.8V supply voltage with 0.18um CMOS process. The transmitter has 800MHz PLL to generate 4 phase clocks. The 4 phase clocks are used for input clock of PRBS and multiplexing. One tap pre-emphasis is used to reduce inter symbol interference (ISI) caused by channel low pass effects. The analog calibration makes the optimized driver impedance independent with the PVT variation.

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