Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 2003.11b
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- Pages.67-70
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- 2003
Analysis and Comparison on Full Adder Block in Deep-Submicron Technology
미세공정상에서 전가산기의 해석 및 비교
Abstract
In this paper the main topologies of one-bit full adders, including the most interesting of those recently proposed, are analyzed and compared for speed, power consumption, and power-delay product. The comparison has been performed on circuits, optimized transistor dimension to minimize power-delay product. The investigation has been carried out with properly defined simulation runs on a Cadence environment using a 0.25-
Keywords