High Performance nFET Operation of Strained-SOI MOSFETs Using Ultra-thin Strained Si/SiGe on Insulator(SGOI) Substrate

초고속 구동을 위한 Ultra-thin Strained SGOI n-MOS 트랜지스터 제작

  • 맹성렬 (한국전자통신연구원 응용소자연구부) ;
  • 조원주 (한국전자통신연구원 응용소자연구부) ;
  • 오지훈 (한국전자통신연구원 응용소자연구부) ;
  • 임기주 (광주 과학기술윈 신소재공학과) ;
  • 장문규 (한국전자통신연구원 응용소자연구부) ;
  • 박재근 (한양대학교 나노 SOI 공정연구실) ;
  • 심태헌 (한양대학교 나노 SOI 공정연구실) ;
  • 박경완 (서울 시립대학교 나노과학과) ;
  • 이성재 (한국전자통신연구원 응용소자연구부)
  • Published : 2003.07.01

Abstract

For the first time, high quality ultra-thin strained Si/SiGe on Insulator (SGOI) substrate with total SGOI thickness( $T_{Si}$ + $T_{SiGe}$) of 13 nm is developed to combine the device benefits of strained silicon and SOI. In the case of 6- 10 nm-thick top silicon, 100-110 % $I_{d,sat}$ and electron mobility increase are shown in long channel nFET devices. However, 20-30% reduction of $I_{d,sat}$ and electron mobility are observed with 3 nm top silicon for the same long channel device. These results clearly show that the FETs operates with higher performance due to the strain enhancement from the insertion of SiGe layer between the top silicon layer and the buried oxide(BOX) layer. The performance degradation of the extremely thin( 3 nm ) top Si device can be attributed to the scattering of the majority carriers at the interfaces.

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