Design a Frequency-to-Digital Converter Using Delay Element

지연소자를 이용한 주파수-디지털 변환회로의 설계

  • 최진호 (부산외국어대학교 컴퓨터공학부) ;
  • 김희정 (부산외국어대학교 컴퓨터공학부)
  • Published : 2003.07.01

Abstract

In this paper, a new CMOS fully integrated frequency-to-digital converter is proposed. The operation of the proposed circuit is based on a pulse-shrinking delay element. In the proposed circuit, a resolution of the converted digital output can be easily improved by increasing the number of the pulse-shrinking element. Also the input frequency range can be easily changed through controlling bias voltage in the pulse-shrinking element. The simulation of the designed circuit carried out by HSPICE using the CMOS 0.35${\mu}{\textrm}{m}$ process technology.

Keywords