한국마이크로전자및패키징학회:학술대회논문집 (Proceedings of the International Microelectronics And Packaging Society Conference)
- 한국마이크로전자및패키징학회 2003년도 International Symposium
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- Pages.165-172
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- 2003
High-density Through-Hole Interconnection in a Silicon Substrate
초록
Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.
키워드