후막 리소그라피 공정을 이용한 내장형 캐패시터 개발에 관한 연구

The Study on the embedded capacitor using thick film lithography

As the size of chip components and module decreases, new patteming method for fine line and geometry is needed. So far, in LTCC(Low Temperature Cofired Ceramic) process, screen printing method has been used generally. But screen printing method has some disadvantages as follows. First, the geometry including line, vias, etc. smaller than $100{\mu}m$ can't be evaluated easily. Second, the patterned dimension is different from designed value, which makes distortion in charactersitics of not only chip components but also modules. Thick film lithography has advantages of thick film screen printing process, low cost and thin film process, fine line feasibility. Using this method, the line with $30{\mu}m$ width and the geometry with expected dimension can be evaluated. In this study, the fine line with $35{\mu}m$ line/space is formed and the embedded capacitor with very small tolerance is developed using thick film lithography.