Design of Synchronous Network System based on SDH

SDH 기반의 동기식 네트워크 시스템 구현

  • Kim, Jeong-Dong (Dept. of Electronics Eng., Myongji Univ.) ;
  • Kwon, J. ;
  • Choi, T. (Dept. of Electronics Eng., Myongji Univ.) ;
  • Huh, W. (Dept. of Electronics Eng., Myongji Univ.) ;
  • Kim, J. (Dept. of Electronics Eng., Myongji Univ.)
  • 김정동 (명지대학교 전자공학과) ;
  • 권정규 ((주)비젼텔레콤) ;
  • 최태종 (명지대학교 전자공학과) ;
  • 허웅 (명지대학교 전자공학과) ;
  • 김정국 (명지대학교 전자공학과)
  • Published : 2002.06.01

Abstract

In this paper, we implemented a SDH synchronous network system based on ITU-T recommendation G.707 - Network node interface for the synchronous digital archy(SDH). For the system, we used signal processing SDH ASIC, and designed a FPGA_Control chip for various signal control and a FPGA_Alignment cllip for data alignment using YHDL(Very high speed integrated circuit Hardware Description Language). For system monitoring, an operation system was developed using ANSI C and executed in CPU (Motorola MPC-860). The system was evaluated by using ANT-20 for data transmission error defection, jitter detection, pointer chocking, and overhead determination.

Keywords