Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2002.06a
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- Pages.417-420
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- 2002
Design of Synchronous Network System based on SDH
SDH 기반의 동기식 네트워크 시스템 구현
- Kim, Jeong-Dong (Dept. of Electronics Eng., Myongji Univ.) ;
- Kwon, J. ;
- Choi, T. (Dept. of Electronics Eng., Myongji Univ.) ;
- Huh, W. (Dept. of Electronics Eng., Myongji Univ.) ;
- Kim, J. (Dept. of Electronics Eng., Myongji Univ.)
- Published : 2002.06.01
Abstract
In this paper, we implemented a SDH synchronous network system based on ITU-T recommendation G.707 - Network node interface for the synchronous digital archy(SDH). For the system, we used signal processing SDH ASIC, and designed a FPGA_Control chip for various signal control and a FPGA_Alignment cllip for data alignment using YHDL(Very high speed integrated circuit Hardware Description Language). For system monitoring, an operation system was developed using ANSI C and executed in CPU (Motorola MPC-860). The system was evaluated by using ANT-20 for data transmission error defection, jitter detection, pointer chocking, and overhead determination.
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