한국전기전자재료학회:학술대회논문집 (Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference)
- 한국전기전자재료학회 2001년도 하계학술대회 논문집
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- Pages.539-542
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- 2001
산화막을 이용한 SiC 기판의 macrostep 형성 억제
Suppression of Macrosteps Formation on SiC Wafer Using an Oxide Layer
초록
In SiC semiconductor device processing, it needs high temperature anneal for activation of ion implanted dopants. The macrosteps, 7~8nm in height, are formed on the surface of SiC substrates during activation anneal. We have investigated the effect of thermally-grown SiO