Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2000.11d
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- Pages.131-134
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- 2000
The Circuit Design and Implementation of HomePNAl.0 Transceiver
HomePNAl.0 Transceiver의 회로 설계 및 구현
- Koo, Ki-Jong (Dept. Of Electronic Engineering, Chungnam National University) ;
- Ryu, Khwang-Hyun (Dept. Of Electronic Engineering, Chungnam National University) ;
- Hong, In-Seong (Dept. Of Electronic Engineering, Chungnam National University) ;
- Kim, Bo-Gwan (Dept. Of Electronic Engineering, Chungnam National University)
- Published : 2000.11.01
Abstract
This paper presents the circuit design and implementation of a HomePNA (Home Phoneline Network Alliance) 1M8 PHY transceiver for specification ver1.1. This paper describes a physical medium interface, an Ethernet MAC controller unit interface, and a management interface of the HomePNA transceiver. The designed HomePNA transceiver can support any specifications having more than 32Mbits/sec(maximum in HomePNA ver2.0) transmission rate by changing physical medium interface, because Ethernet MAC controller unit interface has been designed by using MII.
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