The ASIC Design of the Adaptive De-interlacing Algorithm with Improved Horizontal and Vertical Edges

수평 및 수직 윤곽선을 개선한 ADI(Adaptive De-interlacing) 보간 알고리즘의 ASIC 설계

In this paper, the ADI (Adaptive De-interlacing) algorithm is proposed, which improves visually and subjectively horizontal and vertical edges of the image processed by the ELA(Edge Line-based Average) method. This paper also proposes a VLSI architecture for the proposed algorithm and designed the architecture through the full custom CMOS layout process. The proposed algorithm is verified using C and Matlab and implemented using 0.6$\mu\textrm{m}$ 2-poly 3-metal CMOS standard libraries. For the circuit and logic simulation, Cadence tool is used.