Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
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A Study on the SOI LDMOS with a Tapered Field Plate

경사진 Field Plate을 갖는 SOI LDMOS에 관한 연구

  • Na, Jong-Min (Dept. of Electronics Engineering, Ajou University) ;
  • Choi, Yearn-Ik (Dept. of Electronics Engineering, Ajou University)
  • 나종민 (아주대학교 전자공학과) ;
  • 최연익 (아주대학교 전자공학과)
  • Published : 1995.11.18
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Abstract

An SOI LDMOS(Silicon-On-Insulator Lateral Double diffused MOSPET) with a tapered field plate is proposed and investigated in terms of the breakdown voltage and on-resistance using 2-D simulator, MEDICI. The results of conventional SOI LDMOS with a stepped field plate are reported for the comparison. Simulated breakdown voltage of the proposed LDMOS is found to be higher than that of conventional LDMOS since surface electric field can be reduced due to the field plate over the tapered oxide. On-resistance of proposed LDMOS is found to be lower than that of conventional LDMOS by 10%.

Keywords