대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)
- 대한전기학회 1995년도 추계학술대회 논문집 학회본부
- /
- Pages.299-301
- /
- 1995
3-레벨 인버터를 위한 과전압 제한회로 설계
A Circuit Design for Clamping an Overvoltage in Three-level Inverters
- Jeong, Jae-Houn (Dept. of Electrical Eng., Hanyang Univ.) ;
- Lee, Yo-Han (Dept. of Electrical Eng., Hanyang Univ.) ;
- Hyun, Dong-Seok (Dept. of Electrical Eng., Hanyang Univ.)
- 발행 : 1995.11.18
초록
This paper represents an overvoltage clamping circuit for three level inverters. With a proposed overvoltage clamping circuit, the problems that high voltage stresses and voltage unbalance between outer and inner switches occurs in high power and high voltage 3-level inverters are reduced.
키워드