• Corrosion Science and Technology
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• 제9권6호
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• pp.310-316
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• 2010

Recently a fuel oil of the diesel engine of the marine ship is being changed with heavy oil of low quality as the oil price is higher more and more. Therefore the wear and corrosion in all parts of the engine such as cylinder liner, piston crown, spindle and seat ring of exhaust valves are predominantly increased. In particular the degree of wear and corrosion of piston crown is more seriously compared to the other parts of the engine due to operating in severe environment such as the high temperature of exhaust gas and repeating impact. Thus the repair weldment of the piston crown is a unique method to prolong the its life in a economical point of view. In this case, filler metals having a high corrosion and wear resistance such as stellite 6, Inconel 625 and Inconel 718 are mainly being used for repair welding. However it has been often happened that piston crown on the ship,s job site is being actually inevitably welded with mild filler metals. Therefore in this study, filler metals such as E4301, E4313 and E4316 were welded at SS401 steel as the base metal, and corrosion property of their weld metals in the case of post weld heat treatment or not was investigated with some electrochemical methods such as measurement of corrosion potential, cathodic and anodic polarization curves, cyclic voltammogram and polarization resistance etc. in 0.1% $H_2SO_4$ solution. Corrosion resistance of the weld metal of E4301 was better than the other weld metals in the case of no heat treatment, however, its resistance was considerably decreased with post weld heat treatment(annealing:$625^{\circ}C$, 2 hr) compared to other weld metals. The weld metals of E4313 and E4316 showed a relatively good corrosion resistance by post weld heat treatment.

• 한국전기전자재료학회논문지
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• 제36권3호
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• pp.233-240
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• 2023

p-type Tunnel Oxide Passivating Contacts (TOPCon) solar cell is fabricated with a poly-Si/SiO_x structure. It simultaneously achieves surface passivation and enhances the carriers' selective collection, which is a promising technology for conventional solar cells. The quality of passivation is depended on the quality of the tunnel oxide layer at the interface with the c-Si wafer, which is affected by the bond of SiO formed during the subsequent annealing process. The highest cell efficiency reported to date for the laboratory scale has increased to 26.1%, fabricated by the Institute for Solar Energy Research. The cells used a p-type float zone silicon with an interdigitated back contact (IBC) structure that fabricates poly-Si and SiO_x layer achieves the highest implied open-circuit voltage (iV_oc) is 750 mV, and the highest level of edge passivation is 40%. This review presents an overview of p-type TOPCon technologies, including the ultra-thin silicon oxide layer (SiO_x) and poly-silicon layer (poly-Si), as well as the advancement of the SiO_x and poly-Si layers. Subsequently, the limitations of improving efficiency are discussed in detail. Consequently, it is expected to provide a basis for the simplification of industrial mass production.

• 한국재료학회지
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• 제2권3호
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• pp.180-190
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• 1992

ZMR공정에서 발생하기 쉬운 폴리실리콘의 엉김현상(agglomeration), 슬림, 그리고 실리콘기판이 국부적으로 녹는 현상 등을 방지하기 위한 방법과 재결정화된 박막의 질을 향상시키기 위하여 폴리실리콘과 보호 산화막(capping oxide)두계를 변화시킨 실험 결과를 서술한다. 폴리실리콘의 엉김현상은 폴리실리콘과 보호 산화막 그리고 폴리실리콘과 매몰 산화막(buried oxide)의 계면에서의 wetting각과 관계되는데, 엉김현상을 방지하기 위해서는 암모니아 가스 분위기에서 $1100^{\circ}$C, 3시간 동안 열처리하여 폴리실리콘과 보호 산화막 그리고 폴리실리콘과 매몰 산화막의 계면에 질소를 주입시키면 된다. 실리콘 기판의 뒷면이 국부적으로 녹아 SOI구조가 파괴되는 현상과 슬립은 실리콘 기판의 뒷면을 모래타격(sandblast)하여 약 $20{\mu}m$의 거칠기를 가지도록 했을때 방지할 수 있었다. 재결정화된 폴리실리콘의 두께가 두꺼워짐에 따라 재결정화된 박막에서 subboundary의 간격은 넓어지고, 재결정화된 실리콘 두께의 균일성은 보호 산화막이 두꺼울수록 향상된다. 폴리실리콘의 두께를 $1{\mu}m$로 하였을때 subboundary의 간격은 약 $70-120{\mu}m$정도였고 폴리실리콘의 두께가 $1{\mu}m$이고 보호산화막의 두께가 $2.5{\mu}m$일때, 재결정화 후 실리콘의 두게 균일도는 약 ${\pm}200{\AA}$정도였다.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.