• Journal of Surface Science and Engineering
• /
• v.38 no.3
• /
• pp.106-111
• /
• 2005

Ternary Ti-B-C coatings were synthesized on WC-Co and Si wafers substrates by a PECVD technique using a gaseous mixture of $TiCl_4,\;BCl_3,\;CH_4,\;Ar,\;and\; H_2$. The effects of deposition variables such as substrate temperature, gas ratio, $R_x=[BCl_3/(CH_4+BCl_3)]$ on the microstructure and mechanical properties of Ti-B-C coatings were investigated. From our instrumental analyses, the synthesized Ti-B-C coatings was confirmed to be composites consisting of nanocrystallites TiC, quasi-amorphous TiB2, and amorphous carbon at low boron content, on the contrary, nanocrystallites $TiB_2$, quasi-amorphous TiC, and amorphous carbon at relatively high boron content. The microhardness of the Ti-B-C coatings increased from $\~23 GPa$ of TiC to $\~38 GPa$ of $Ti_{0.33}B_{0.55}C_{0.11}$ coatings with increasing the boron content. The $Ti_{0.33}B_{0.55}C_{0.11}$ coatings showed lower average friction coefficient of 0.45, in addition, it showed relatively better wear behavior compared to other binary coatings of $TiB_2$ and TiC. The microstruture and microhardness value of Ti-B-C coatings were largely depend on the deposition temperature.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.26 no.3
• /
• pp.246-251
• /
• 2013

Screen printing is commonly used to form the front/back electrodes in silicon solar cell. But it has caused high resistance and low aspect ratio, resulting in decreased conversion efficiency in solar cell. Recently the plating method has been combined with screen-printed c-Si solar cell to reduce the resistance and improve the aspect ratio. In this paper, we investigated the effect of light induced silver plating with screen-printed c-Si solar cells and compared their electrical properties. All wafers were textured, doped, and coated with anti-reflection layer. The metallization process was carried out with screen-printing, followed by co-fired. Then we performed light induced Ag plating by changing the plating time in the range of 20 sec~5min with/without external light. For comparison, we measured the light I-V characteristics and electrode width by optical microscope. During plating, silver ions fill the porous structure established in rapid silver particle sintering during co-firing step, which results in resistance decrease and efficiency improvement. The plating rate was increased in presence of light lamp, resulting in widening the electrode with and reducing the short-circuit current by shadowing loss. With the optimized plating condition, the conversion efficiency of solar cells was increased by 0.4% due to decreased series resistance. Finally we obtained the short-circuit current of 8.66 A, open-circuit voltage of 0.632 V, fill factor of 78.2%, and efficiency of 17.8% on a silicon solar cell.

• Proceedings of the KIEE Conference
• /
• 2007.07a
• /
• pp.1542-1543
• /
• 2007

This paper presents the effect of driving waveform for piezoelectric bend mode inkjet printhead with optimized mechanical design. Experimental and theoretical studies on the applied driving waveform versus jetting characteristics were performed. The inkjet head has been designed to maximize the droplet velocity, minimize voltage response of the actuator and optimize the firing frequency to eject ink droplet. The head design was carried out by using mechanical simulation. The printhead has been fabricated with Si(100) and SOI wafers by MEMS process and silicon direct bonding method. To investigate how performance of the piezoelectric ceramic actuator influences on droplet diameter and droplet velocity, the method of stroboscopy was used. Using the water based ink of viscosity of 11.8 cps and surface tension of 0.025N/m, it is possible to eject stable droplets through 64 nozzles average velocity of 4.05 m/s with standard deviation of 0.06 m/s and average diameter of $29.2\;{\mu}m$ with standard variation of $0.5\;{\mu}m$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.06a
• /
• pp.8-9
• /
• 2006

Hafnium oxide ($HfO_2$) thin films were deposited on p-type (100) silicon wafers by atomic layer deposition (ALD) using TEMAHf and $O_3$. Prior to the deposition of $HfO_2$ films, a thin Hf ($10\;{\AA}$) metal layer was deposited. Deposition temperature of $HfO_2$ thin film was $350^{\circ}C$ and its thickness was $150\;{\AA}$. Samples were then annealed using furnace heating to temperature ranges from 500 to $900^{\circ}C$. The MOS capacitor of round-type was fabricated on Si substrates. Thermally evaporated $3000\;{\AA}$-thick AI was used as top electrode. In this work, We study the interface characterization of $HfO_2$/Hf/Si MOS capacitor depending on annealing temperature. Through AES(Auger Electron Spectroscopy), capacitance-voltage (C-V) and current-voltage (I-V) analysis, the role of Hf layer for the better $HfO_2$/Si interface property was investigated. We found that Hf meta1 layer in our structure effective1y suppressed the generation of interfacial $SiO_2$ layer between $HfO_2$ film and silicon substrate.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.06a
• /
• pp.169-170
• /
• 2006

In this study, ultra thin films of ferroelectric vinylidene fluoride-trifluoroethylene (VF2-TrFE) copolymer were fabricated on degenerated Si (n+, $0.002\;{\Omega}{\cdot}cm$) using by spin coating method. A 1~5 wt% diluted solution of purified vinylidene fluoride-trifluoroethylene (VF2:TrFE=70:30) in a dimethylformamide (DMF) solvent were prepared and deposited on silicon wafers at a spin rate of 2000~5000rpm for 30 seconds. After annealing in a vacuum ambient at $200^{\circ}C$ for 60 min, upper gold electrodes were deposited by vacuum evaporation for electrical measurement. X-ray diffraction results showed that the VF2-TrFE films on Si substrates had $\beta$-phase of copolymer structures. The capacitance on $n^+$-Si(100) wafer showed hysteresis behavior like a butterfly shape and this result indicates clearly that the dielectric films have ferroelectric properties. The typical measured remnant polarization (2Pr) and coercive filed (EC) values measured using a computer controlled a RT-66A standardized ferroelectric test system (Radiant Technologies) were about $0.54\;C/cm^2$ and 172 kV/cm, respectively, in an applied electric field of ${\pm}0.75\;MV/cm$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.24 no.3
• /
• pp.240-244
• /
• 2011

The high cost of crystalline silicon solar cells has been considered as one of the major obstacles to their terrestrial applications. Spin on doping (SOD) is presented as a useful process for the manufacturing of low cost solar cells. Phosphorus (P509) was used as an n-type emitters of solar cells. N-type emitters were formed on p-type EFG ribbon Si wafers by using a SOD at different spin speed (1,000~4,000 rpm), diffusion temperatures ($800^{\circ}C{\sim}950^{\circ}C$), and diffusion time (5~30 min) in $N_2+O_2$ atmosphere. With optimum condition, we were able to achieve cell efficiency of 14.1%.

• Polymer(Korea)
• /
• v.28 no.4
• /
• pp.328-334
• /
• 2004

A series of methoxy poly(ethylene glycol) (MPEG)-poly(L-lactide-co-glycolide) (PLGA) diblock copolymers were synthesized by ring-opening polymerization of L-lactide and glycolide with carbitol (134 g/mole) or different molecular weights of MPEG (550, 2000, and 5000 g/mole) as an initiator in presence of Sn(Oct)$_2$. The properties of diblock copolymers were characterized by using $^1$H-NMR, GPC, and XRD. After uniform mixing of block copolymers and 1% albumin bovine-fluorescein isothiocyanate(FITC-BSA) with a freeze miller, the wafers loaded FITC-BSA were fabricated by using a mold with a dimensions of 3 mm${\times}$1mm diameter. The release profiles of FITC-BSA and the pH changes of wafer were examined using pH 7.4 PBS for 30 days at 37$^{\circ}C$. The release profiles of albumin showed fast initial burst as the molecular weights of MPEG increased. As a result of this study, the release behavior of BSA was controlled with introducing MPEG in the block copolymers.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.464-464
• /
• 2010

A few years ago, for maintaining high stability and production yield of production equipment in a semiconductor fab, on-line monitoring of wafers is required, so that semiconductor manufacturers are investigating a software based process controlling scheme known as virtual metrology (VM). As semiconductor technology develops, the cost of fabrication tool/facility has reached its budget limit, and reducing metrology cost can obviously help to keep semiconductor manufacturing cost. By virtue of prediction, VM enables wafer-level control (or even down to site level), reduces within-lot variability, and increases process capability, $C_{pk}$. In this research, we have practiced VM on $SiO_2$ etch rate with optical emission spectroscopy(OES) data acquired in-situ while the process parameters are simultaneously correlated. To build process model of $SiO_2$ via, we first performed a series of etch runs according to the statistically designed experiment, called design of experiments (DOE). OES data are automatically logged with etch rate, and some OES spectra that correlated with $SiO_2$ etch rate is selected. Once the feature of OES data is selected, the preprocessed OES spectra is then used for in-situ sensor based VM modeling. ICP-RIE using 葰.56MHz, manufactured by Plasmart, Ltd. is employed in this experiment, and single fiber-optic attached for in-situ OES data acquisition. Before applying statistical feature selection, empirical feature selection of OES data is initially performed in order not to fall in a statistical misleading, which causes from random noise or large variation of insignificantly correlated responses with process itself. The accuracy of the proposed VM is still need to be developed in order to successfully replace the existing metrology, but it is no doubt that VM can support engineering decision of "go or not go" in the consecutive processing step.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.9-10
• /
• 2010

Since the discovery of graphene by mechanical exfoliation from graphite[1], various fabrication methods are available today such as chemical exfoliation, epitaxial graphene on SiC substrates, etc. In view of industrialization, the mechanical exfoliation method may not be an option. Epitaxial graphene on SiC substrates, in this respect, is by far more practical because the method consists of conventional thermal treatments familiar to semiconductor industry. Still, the use of the SiC substrate itself, and hence the incompatibility with the Si technology, lessens the importance of this technology in its future industrialization. In this context, we have tackled the problem of forming graphene on Si substrates (GOS). Our strategy is to form an ultrathin (~80 nm) SiC layer on top of a Si substrate, and to graphitize the top SiC layers by a vacuum annealing. We have actually succeeded in forming the GOS structure [2,3,4]. Raman-scattering microscopy indicates presence of few-layer graphene (FLG) formed on our annealed SiC/Si heterostructure, with the G ($1580\;cm^{-1}$) and the G'($2700\;cm^{-1}$) bands, both related to ideal graphene, clearly observed. Presence of the D ($1350\;cm^{-1}$) band indicates presence of defects in our GOS films, whose elimination remains as a challenge in the future. To obtain qualified graphene films on Si substrate, formation of qualified SiC films is crucial in the first place, and is achieved by tuning the growth parameters into a process window[5]. With a potential for forming graphene films on large-scale Si wafers, GOS is a powerful candidate as a key technology in bringing graphene into silicon technology.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.322-322
• /
• 2010

For boron doping on n-type silicon wafer, around $1,000^{\circ}C$ doping temperature is required, because of the relatively low solubility of boron in a crystalline silicon comparing to the phosphorus case. Boron doping by fiber laser annealing and lamp furnace heat treatment were carried out for the uniformly deposited p-a-Si:H layer. Since the uniformly deposited p-a-Si:H layer by cluster is highly needed to be doped with high temperature heat treatment. Amorphous silicon layer absorption range for fiber laser did not match well to be directly annealed. To improve the annealing effect, we introduce additional lamp furnace heat treatment. For p-a-Si:H layer with the ratio of $SiH_4:B_2H_6:H_2$=30:30:120, at $200^{\circ}C$, 50 W power, 0.2 Torr for 30 min. $20\;mm\;{\times}\;20\;mm$ size fiber laser cut wafers were activated by Q-switched fiber laser (1,064 nm) with different sets of power levels and periods, and for the lamp furnace annealing, $980^{\circ}C$ for 30 min heat treatment were implemented. To make the sheet resistance expectable and uniform as important processes for the $p^+$ layer on a polished n-type silicon wafer of (100) plane, the Q-switched fiber laser used. In consequence of comparing the results of lifetime measurement and sheet resistance relation, the fiber laser treatment showed the trade-offs between the lifetime and the sheet resistance as $100\;{\omega}/sq.$ and $11.8\;{\mu}s$ vs. $17\;{\omega}/sq.$ and $8.2\;{\mu}s$. Diode level device was made to confirm the electrical properties of these experimental results by measuring C-V(-F), I-V(-T) characteristics. Uniform and expectable boron heavy doped layers by fiber laser and lamp furnace are not only basic and essential conditions for the n-type crystalline silicon solar cell fabrication processes, but also the controllable doping concentration and depth can be established according to the deposition conditions of layers.