• Journal of the Korean Crystal Growth and Crystal Technology
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• v.26 no.5
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• pp.171-174
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• 2016

The diamond wire sawing method to produce silicon wafers for the photovoltaic application is still a new and highly investigated wafering technology. This technology, featured as the higher productivity, lower wear of the wire, and easier recycling of the coolant, is expected to become the mainstream technique for slicing the silicon crystals. However, the saw marks on the wafer surface have to be investigated and improved. This paper discusses the removal of saw marks on diamond wire-sawn single crystalline silicon wafer. With a pretreatment step using tetramethyl ammonium hydroxide ($(CH_3)_4NOH$, TMAH) and conventional texturing process with KOH solution (1 % KOH, 8 % IPA, and DI water), the saw marks on the surface of the diamond wire-sawn silicon wafers can be effectively removed and they are invisible to naked eyes completely.

• Biotechnology and Bioprocess Engineering:BBE
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• v.8 no.4
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• pp.240-245
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• 2003

The use of microfabricated microfluidic devices offers significant advantages over current technologies including fast analysis time and small reagent requirements. In the context of proteomic research, the possibility of using affinity-based separations for prefractionation of samples using microfluidic devices has significant potential. We demonstrate the use of microscale devices to achieve affinity separations of proteins using a device fabricated from borosilicate glass wafers. Photolithography and wet etching are used to pattern individual glass wafers and the wafers are fusion bonded at 650$^{\circ}C$ to obtain enclosed channels. A polymer has been successfully polymerized in situ and used either as a frit for packing beads or, when derivatized with Cibacron Blue 3GA, as a separation matrix. Both of these technologies are based on in situ UV photopolymerization of glycidyl methacrylate (GMA) and trimethylolpropane trimethacrylate (TRIM) in channels.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.3 s.96
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• pp.78-83
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• 1999

The bonding interface is dependent on the properties of surfaces prior to SDB(silicon wafer direct bonding). In this paper, we prepared silicon surfaces in several chemical solutions, and annealed bonding wafers which were combined with thermally oxidized wafers and bare silicon wafers in the temperature range of $600{\times}1000^{\circ}C$. After bonding, the bonding interface is investigated by an infrared(IR) topography system which uses the penetrability of infrared through silicon wafer. Using this procedure, we observed intrinsic bubbles at elevated temperatures. So, we verified that these bubbles are related to cleaning and drying conditions, and the interface oxides on silicon wafer reduce the formation of intrinsic bubbles.

• Journal of the Korean Society for Nondestructive Testing
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• v.36 no.1
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• pp.1-8
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• 2016

Single crystalline silicon wafers having (100), (110), and (111) directions are employed as specimens for obtaining slowness profiles. Leaky Lamb waves (LLW) from immersed wafers were detected by varying the incident angles of the specimens and rotating the specimens. From an analysis of LLW signals for different propagation directions and phase velocities of each specimen, slowness profiles were obtained, which showed a unique symmetry with different symmetric axes. Slowness profiles were compared with elastic moduli of each wafer. They showed the same symmetries as crystal structures. In addition, slowness profiles showed expected patterns and values that can be inferred from elastic moduli. This implies that slowness profiles can be used to examine crystal structures of anisotropic solids.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.21 no.5
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• pp.187-192
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• 2011

Tilt angle of r-plane wafer is a one of the important factors related with the quality of the GaN epi, so the fine control of the tilt angle is important for the growing of high quality non-polar a-GaN epi. We prepared the R-plane sapphire wafers with slight tilt angles for nonpolar a-plane GaN. The target tilt angles of ${\alpha}$ and ${\beta}$ were 0, -0.1, -0.15, -0.2, -0.4, $-0.6^{\circ}$ and -0.1, 0, $0.1^{\circ}$, respectively. The tilt angles of sliced R-plane sapphire wafers were measured by x-ray and the statistical evaluation of reliability of tilt angles of wafers were performed. The tolerance of the tilt angle was ${\pm}0.03^{\circ}$. R-plane sapphire wafers have relatively large distributions of BOW and TTV data than c-plane sapphire wafers due to the large anisotropy of R-plane. As the tilt angle ${\alpha}$ was increased from -0.1 to $-0.6^{\circ}$, the step widths and heights were decreased from 156 nm to 26 nm and 0.4 nm to 0.2 nm, respectively. The growth and qualities of GaN epi seems to be largely affected by the change of step structure of R-plane sapphire wafers with tilt angle.

• Polymer(Korea)
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• v.29 no.5
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• pp.468-474
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• 2005

PLGA and PCL copolymers initiated by carbitol as drug carriers were synthesized by ring-opening polymerization of L-lactide (LA), glycolide (GA), and $\varepsilon-caprolactone(\varepsilon-CL)$. Implantable wafers were simply fabricated by direct compression method after physical mixing of copolymers and bovine serum albumin-fluorescein isothiocyanate (BSA-FITC) as a model protein drug. The release amounts of BSA-FITC from wafers were determined by fluorescence intensity using the fluorescence spectrophotometer. Also, the release behavior of BSA-FITC on wafers was controlled by adding the additives such as collagen, small intestinal submucosa (SIS), poly(vinyl pyrrolidone) (PVP), and poly(thylene glycol) (PEG). The wafer prepared by PLGA and PCL exhibited slow release within $10\%$ for 30 days. But, those prepared by a variety of additives exhibited the controlled BSA release patterns with a dependence on the additive contents. furthermore, the wafers containing natural materials such as collagen and SIS showed more zero-order release profile than that with synthetic materials such as PVP and PEG. It was confirmed that the release of BSA from implantable wafers could be easily controlled by adding natural additives.

• Journal of the Korean Ceramic Society
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• v.29 no.11
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• pp.863-869
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• 1992

A SOG(spin glass) solution with excellent wetting to Si wafers was prepared by acid-hydrolysis of Si(OEt)4 and Me2Si(OEt)2. The solution was spin coated on Si wafers, and effects of heat treatment of the film were characterized by TG/DTA, FTIR and Ellipsometry. Silica film was obtained by heat treatment at $600^{\circ}C$ within one hour, but heat treatment at 80$0^{\circ}C$ caused interfacial oxidation of the silicon substrate. Unexpectedly silica films with much better adhesion were obtained by curing at $600^{\circ}C$ for over 30 min. than those obtained by thermal oxidation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.578-581
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• 2001

Silicon wafers using DRAM devices required for high cleaning technology and this cleaning technology was evaluated by defect level or electron life time. This paper examined the correlation of SPV(Surface Photo Voltaic Analyzer) which analyzes diffusion length of minority carriers and DLTS(Deep level Transient Spectroscope) which analyzes defect level.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.55.4-55
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• 2002

In the semiconductor fabrication, particle contamination is wide-spread and one of major causes to yield loss. Extensive testing has revealed that even careful handling of wafers during processing may cause photo-resist materials to flake off wafer edges. So, to remove the photo-resist at the outer 5mm of wafers, UV(Ultraviolet) rays are exposed. WEE (Wafer Edge Exposure) process station is the system that exposes the wafer edge as prespecified by controlling the positioning mechanism and maintaining the light intensity level In this work, WEE process station has been designed so as to significantly lower the amount of particle contamination which occurs even during the most r...

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.375-378
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• 1988

In this paper a newly designed rapid thermal process (RTP) structure is proposed to the slip induced in silicon wafers considerably. The reflectors and a graphite radiation were used to compensate the temperature difference causing slip in silicon wafers. From our experiments it is known that slip can be removed during a rapid thermal annealing at high temperature.