• Journal of the Korean Crystal Growth and Crystal Technology
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• v.18 no.4
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• pp.137-139
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• 2008

Floating zone, neutron transmutation-doped and magnetic Czochralski silicon crystals are being widely used for fabrication power devices. To improve the quality of these devices and to decrease their production cost, it is necessary to use large-diameter wafers with high and uniform resistivity. Recent developments in the crystal growth technology of Czochralski silicon have enable to produce Czochralski silicon wafers with sufficient resistivity and with well-controlled, suitable concentration of oxygen. In addition, using Czoehralski silicon for substrate materials may offer economical benefits, First, Czoehralski silicon wafers might be cheaper than standard floating zone silicon wafers, Second, Czoehralski wafers are available up to diameter of 300 mm. Thus, very large area devices could be manufactured, which would entail significant saving in the costs, In this work, the conventional Czochralski silicon crystals were grown with higher oxygen concentrations using high pure polysilicon crystals. The silicon wafers were annealed by several steps in order to obtain saturated oxygen precipitation. In those wafers high resistivity over $5,000{\Omega}$ cm is kept even after thermal donor formation annealing.

• Transactions on Electrical and Electronic Materials
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• v.2 no.3
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• pp.24-27
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• 2001

The end point of oxide chemical mechanical polishing (CMP) have determined by polishing time calculated from removal rate and target thickness of oxide. This study is about control of oxide removal amounts on the shallow trench isolation (STI) patterned wafers using removal rate and thickness of blanket (non-patterned) wafers. At first, it was investigated the removal properties of PETEOS blanket wafers, and then it was compared with the removal properties and the planarization (step height) as a function of polishing time of the specific STI patterned wafers. We found that there is a relationship between the oxide removal amounts of blanket and patterned wafers. We analyzed this relationship, and the post CMP thickness of patterned wafers could be controlled by removal rate and removal target thickness of blanket wafers. As the result of correlation analysis, we confirmed that there was the strong correlation between patterned and blanket wafer (correlation factor: 0.7109). So, we could confirm the repeatability as applying for STI CMP process from the obtained linear formula. As the result of repeatability test, the differences of calculated polishing time and actual polishing time was about 3.48 seconds. If this time is converted into the thickness, then it is from 104 $\AA$ to 167 $\AA$. It is possible to be ignored because process margin is about 1800 $\AA$.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.295-298
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• 2015

Ozone micro-bubble cleaning system was designed, and made to develop a unique technique to clean wafers by using ozone micro-bubbles. The ozone micro-bubble cleaning system consisted of loading, cleaning, rinsing, drying and un-loading zones, respectively. In case of the cleaning the silicon wafers of a solar cell, more than 99 % of cleaning efficiency was obtained by dipping the wafers at 10 ppm of ozone for 10 minutes. Both of long cleaning time and high ozone concentration in the wet-solution with ozone micro-bubbles reduced cleaning efficiency because of the re-sorption of debris. The cleaning technique by ozone micro-bubbles can be also applied to various wafers for an ingot and LED as an eco-friendly method.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.2
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• pp.218-223
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• 2004

The sapphire wafers for blue light emitting devices were manufactured by the implementation of the surface machining technology based on micro-tribology. This process has been performed by Micro-lapping process. The sapphire crystalline wafers were characterized by double crystal X-ray diffraction. The sample quality of crystalline sapphire wafer at surface has a full width at half maximum of 250 arcsec. This value at the surface sapphire wafer surfaces indicated 0.12${mu}m$ sizes. Surfaces of sapphire wafers were mechanically affected by residual stress and surface default. As a result, the value of surface roughness of sapphire wafers measured by AFM(Atom Force Microscope) was 2.1nm.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.82-85
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• 2003

The sapphire wafers for blue light emitting devices were manufactured by the implementation of the surface machining technology based on micro-tribology. This process has been performed by Micro-lapping process. The sapphire crystalline wafers were characterized by DCXD(Double Crystal X-ray Diffraction). The sample quality of crystalline sapphire wafer at surface has a FWHM(Full Width at Half Maximum) of 250 arcsec. This value at the sapphire wafer surfaces indicated 0.12${\mu}{\textrm}{m}$ sizes. Surfaces of sapphire wafers were mechanically affected by residual stress and surface default. Also Surfaces roughness of sapphire wafers were measured 2.1 by AFM(Atom Force Microscope).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05b
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• pp.31-34
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• 2003

The sapphire wafers for blue light emitting devices were manufactured by the implementation of the surface machining technology based on micro-tribology. This process has been performed by chemical and mechanical polishing(CMP) process. The sapphire crystalline wafers were characterized by double crystal X-ray diffraction. The sample quality of sapphire crystalline wafer at surfaces has a full width at half maximum 89 arcses. The surfaces of sapphire wafers were mechanically affected by residual stress and surface default. Sapphire wafers's waveness has higher abrasion rate in the edge of the wafer than its center due to Newton's Ring interference.

• Proceedings of the SAREK Conference
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• 2007.11a
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• pp.600-605
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• 2007

In this study, the risk rates of different contamination sources of the Foreign material in a minienvironment were analyzed through CFD simulation. From the results, the ambient contamination sources mainly affect wafers in the FOUP, whereas the internal contamination sources mainly affect wafers laid on the robot arm in the minienvironment. And the purging plenum system is very useful in protecting the wafers in the FOUP from Foreign materials transferred from the FFU. However, this system is unable to protect the wafers on the robot arm from internal Foreign materials and the wafers in the FOUP from sources of the interface between the FOUP and the minienvironment.

• Particle and aerosol research
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• v.14 no.4
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• pp.181-189
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• 2018

In this study, the risk rates of different contamination sources of the contaminant in a minienvironment were analyzed through Computational Fluid Dynamics (CFD) simulation. The airflow pattern characteristics can only predict the qualitative variation of contaminant concentration, but cannot evaluate the quantitative variations in the risk rate of sources. From the results, the ambient contamination sources mainly affect wafers in the Front Opening Unified Pod (FOUP), whereas the internal contamination sources mainly affect wafers laid on the robot arm in the minienvironment. And the purging plenum system is very useful in protecting the wafers in the FOUP from contaminants transferred from the Fan Filter Unit (FFU). However, this system is unable to protect the wafers on the robot arm from internal contaminants and the wafers in the FOUP from sources of the interface between the FOUP and the minienvironment.

• Transactions on Electrical and Electronic Materials
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• v.14 no.4
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• pp.203-207
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• 2013

P-type Si wafers were dipped in HF solution. The minority carrier lifetime (lifetime) increased after HF treatment due to the hydrogen termination effect. To investigate the film passivation effect, PECVD was used to deposit $SiN_x$ on both HF-treated and untreated wafers. $SiN_x$ generally helped to improve the lifetime. A thermal process at $850^{\circ}C$ reduced the lifetime of all wafers because of the dehydrogenation at high temperature. However, the HF-treated wafers showed better lifetime than untreated wafers. PERCs both passivated and not passivated by HF treatment were fabricated on the rear side, and their characteristics were measured. The short-circuit current density and the open-circuit voltage were improved due to the effectively increased lifetime by HF treatment.

• Journal of the Korean Operations Research and Management Science Society
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• v.18 no.1
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• pp.119-126
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• 1993

We study a manufacturing process that is quite common in semiconductor wafer fabrication of semiconductor chip production. A machine is used to process a job consisting of J wafers. Each job requires a setup, and the i$_{th}$ setup for a job is sucessful with probability P$_{i}$. The setup is prone to failure, which results in the loss of expensive wafers. Therefore, a tiral run is first conducted on a small batch. If the set up is successful, the test is passed and the balance of the job can be processed. If the setup is unsuccessful, the exposed wafers are lost to scrap and the mask is realigned. The process then repeats on the balance of the job. We call this as send-ahead policy and consider general policies in which the number of wafers that are sent shead depend on the cost of the raw wafer, the sequence of success probabilities, and the balance of the job. We model this process and determine the expected number of good wafers per job,the expected time to process a job, and the long run average throughput. An algorithm to minimize the cost per good wafer subject to a demand constraint is provided.d.d.