• Korean Chemical Engineering Research
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• 제45권5호
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• pp.466-472
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• 2007

웨이퍼 레벨(WL) 3차원(3D) 집적을 구현하기 위해 저유전체 고분자를 본딩 접착제로 이용한 웨이퍼 본딩과, 적층된 웨이퍼간 전기배선 형성을 위해 구리 다마신(damascene) 공정을 사용하는 방법을 소개한다. 이러한 방법을 이용하여 웨이퍼 레벨 3차원 칩의 특성 평가를 위해 적층된 웨이퍼간 3차원 비아(via) 고리 구조를 제작하고, 그 구조의 기계적, 전기적 특성을 연속적으로 연결된 서로 다른 크기의 비아를 통해 평가하였다. 또한, 웨이퍼간 적층을 위해 필수적인 저유전체 고분자 수지를 이용한 웨이퍼 본딩 공정의 다음과 같은 특성 평가를 수행하였다. (1) 광학 검사에 의한 본딩된 영역의 정도 평가, (2) 면도날(razor blade) 시험에 의한 본딩된 웨이퍼들의 정성적인 본딩 결합력 평가, (3) 4-점 굽힘시험(four point bending test)에 의한 본딩된 웨이퍼들의 정량적인 본딩 결합력 평가. 본 연구를 위해 4가지의 서로 다른 저유전체 고분자인 benzocyclobutene(BCB), Flare, methylsilsesquioxane(MSSQ) 그리고 parylene-N을 선정하여 웨이퍼 본딩용 수지에 대한 적합성을 검토하였고, 상기 평가 과정을 거쳐 BCB와 Flare를 1차적인 본딩용 수지로 선정하였다. 한편 BCB와 Flare를 비교해 본 결과, Flare를 이용하여 본딩된 웨이퍼들이 BCB를 이용하여 본딩된 웨이퍼보다 더 높은 본딩 결합력을 보여주지만, BCB를 이용해 본딩된 웨이퍼들은 여전히 칩 back-end-of-the-line (BEOL) 공정조건에 부합되는 본딩 결합력을 가지는 동시에 동공이 거의 없는 100%에 가까운 본딩 영역을 재현성있게 보여주기 때문에 본 연구에서는 BCB가 본딩용 수지로 더 적합하다고 판단하였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1988년도 한국자동제어학술회의논문집(국내학술편); 한국전력공사연수원, 서울; 21-22 Oct. 1988
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• pp.353-359
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• 1988

In this paper, the design and implementation of a multi-processor based die bonder machine for the semiconductor will be described. This is a final research results carried out for two years from June, 1986 to July, 1988. The mechanical system consists of three subsystems such as bonding head module, wafer feeding module, and lead frame feeding module. The overall control system consists of the following three subsystems each of which employs a 16 bit microprocessor MC 68000 : (i) supervisory control system, (ii) visual recognition / inspection system and (iii) the display system. Specifically, the supervisory control system supervises the whole sequence of die bonder machine, performs a self-diagnostics while it controls the bonding head module according to the prespecified bonding cycle. The vision system recognizes the die to inspect the die quality and deviation / orientation of a die with respect to a reference position, while it controls the wafer feeding module. Finally, the display system performs a character display, image display ans various error messages to communicate with operator. Lead frame feeding module is controlled by this subsystem. It is reported that the proposed control system were applied to an engineering sample and tested in real-time, and the results are sucessful as an engineering sample phase.

• International Journal of Control, Automation, and Systems
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• 제4권3호
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• pp.372-381
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• 2006

The purpose of this study was to develop a process management system to manage ingot fabrication and improve ingot quality. The ingot is the first manufactured material of wafers. Trace parameters were collected on-line but measurement parameters were measured by sampling inspection. The quality parameters were applied to evaluate the quality. Therefore, preprocessing was necessary to extract useful information from the quality data. First, statistical methods were used for data generation. Then, modeling was performed, using the generated data, to improve the performance of the models. The function of the models is to predict the quality corresponding to control parameters. Secondly, rule extraction was performed to find the relation between the production quality and control conditions. The extracted rules can give important information concerning how to handle the process correctly. The dynamic polynomial neural network (DPNN) and decision tree were applied for data modeling and rule extraction, respectively, from the ingot fabrication data.

• 제어로봇시스템학회논문지
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• 제14권6호
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• pp.519-522
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• 2008

As industry of a semiconductor and LCD industry have been rapidly growing, precision technologies of machining such as etching and 3D measurement are required. Stylus has been important measuring method in traditional manufacturing process. However, its disadvantages are low measuring speed and damage possibility at contacting point. To overcome mentioned disadvantage, non-contacting measurement method is needed such as PMP(Phase Measuring Profilometry), WSI(white scanning interferometer) and Confocal Profilometry. Among above 3 well-known methods, WSI started to be applied to FPD(flat panel display) manufacturing process. Even though it overcomes 21t ambiguity of PMP method and can measure objects which has specular surface, the measuring speed and vibration coming from manufacturing machine are one of main issue to apply full automatic total inspection. In this study, We develop high speed WSI system and algorithm to reduce unknown noise. The developing WSI and algorithm are implemented to measure 3D surface of wafer. Experimental results revealed that the proposed system and algorithm are able to measure 3D surface profile of wafer with a good precision and high speed.

• Smart Structures and Systems
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• 제1권2호
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• pp.185-215
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• 2005

Advanced signal processing techniques have been long introduced and widely used in structural health monitoring (SHM) and nondestructive evaluation (NDE). In our research, we applied several signal processing approaches for our embedded ultrasonic structural radar (EUSR) system to obtain improved damage detection results. The EUSR algorithm was developed to detect defects within a large area of a thin-plate specimen using a piezoelectric wafer active sensor (PWAS) array. In the EUSR, the discrete wavelet transform (DWT) was first applied for signal de-noising. Secondly, after constructing the EUSR data, the short-time Fourier transform (STFT) and continuous wavelet transform (CWT) were used for the time-frequency analysis. Then the results were compared thereafter. We eventually chose continuous wavelet transform to filter out from the original signal the component with the excitation signal's frequency. Third, cross correlation method and Hilbert transform were applied to A-scan signals to extract the time of flight (TOF) of the wave packets from the crack. Finally, the Hilbert transform was again applied to the EUSR data to extract the envelopes for final inspection result visualization. The EUSR system was implemented in LabVIEW. Several laboratory experiments have been conducted and have verified that, with the advanced signal processing approaches, the EUSR has enhanced damage detection ability.

• Applied Microscopy
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• 제52권
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• pp.1.1-1.8
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• 2022

As semiconductor device architecture develops, from planar field-effect transistors (FET) to FinFET and gate-all-around (GAA), there is an increased need to measure 3D structure sidewalls precisely. Here, we present a 3-Dimensional Atomic Force Microscope (3D-AFM), a powerful 3D metrology tool to measure the sidewall roughness (SWR) of vertical and undercut structures. First, we measured three different dies repeatedly to calculate reproducibility in die level. Reproducible results were derived with a relative standard deviation under 2%. Second, we measured 13 different dies, including the center and edge of the wafer, to analyze SWR distribution in wafer level and reliable results were measured. All analysis was performed using a novel algorithm, including auto fattening, sidewall detection, and SWR calculation. In addition, SWR automatic analysis software was implemented to reduce analysis time and to provide standard analysis. The results suggest that our 3D-AFM, based on the tilted Z scanner, will enable an advanced methodology for automated 3D measurement and analysis.

• 한국위성정보통신학회논문지
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• 제1권2호
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• pp.56-62
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• 2006

본 논문에서는 통신해양기상위성 Ka대역 위성통신중계기에 사용하기 위해 개발한 MMIC의 인증 시험에 대해 다루었다. 통신해양기상위성의 통신중계기에 사용될 Ka대역 능동부품은 총 12종의 MMIC를 이용하여 개발되었다. 12종의 MMIC중에는 저잡음 증폭기, 중전력 증폭기, 주파수 혼합기, 주파수 체배기, RF 스위치, 그리고 감쇄기 기능을 갖는 MMIC들이 포함되어 있다. MMIC의 제조 공정은 우주 인증된 시설인 미국 NGST사의 0.15um GaAs pHEMT공정을 이용하였으며, 지난 수십년간 많은 우주 산업 관련 부품 생산 경험을 가지고 있다. 제작된 모든 MMIC에 대하여 Visual Inspection을 수행하였으며, Wafer Lot Acceptance 판정을 위하여 SEM(Scanning Electron Microscope) Inspection을 수행하였다. MMIC의 동작 수명을 보증하기 위해 Test Fixture를 제작하여 $125^{\circ}C$의 온도에서240시간 동안의 Burn-in 시험과 1000시간 동안의 가속 수명 시험이 수행되었다. MMIC 부품의 성능 저하 또는 수명 단축의 가장 큰 요인인 pHEMT의 채널온도 상승을 확인하기 위하여 적외선 온도 측정 시험과 유한요소법을 이용한 pHEMT의 채널 온도 해석을 수행하였다.

• 방사선산업학회지
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• 제8권3호
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• pp.147-153
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• 2014

This paper describes a large area CMOS image sensor module Implementation using the precision align inspection program. This work is needed because wafer cutting system does not always have high precision. The program check more than 8 point of sensor edges and align sensors with moving table. The size of a $2{\times}1$ butted CMOS image sensor module which except for the size of PCB is $170mm{\times}170mm$. And the pixel size is $55{\mu}m{\times}55{\mu}m$ and the number of pixels is $3,072{\times}3,072$. The gap between the two CMOS image sensor module was arranged in less than one pixel size.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 1998년도 춘계학술대회논문집; 용평리조트 타워콘도, 21-22 May 1998
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• pp.302-307
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• 1998

In the production of semiconductor wafer, optical and electron microscopes, ion-beam, laser device must maintain their alignments within a sub-micrometer. This equipment requires a vibration free environment to provide its proper function. Especially, lithography and inspection devices, which have sub-nanometer class high accuracy and resolution, have come to necessity for producing more improved giga and tera class semiconductor wafers. This high technology equipments require very strict environmental vibration standard, vibration criteria, in proportion to the accuracy of the manufacturing, inspecting devices. The vibration criteria of high sensitive equipment should be represented in the form of exactness and accuracy, because this is used as basic data for the design of building structure and structural dynamics of equipment. The study on the evaluation of the factors affecting the permissible vibration criteria is required to design the efficient isolation system of the semiconductor manufacturing of equipment. This paper deals with the properties of the effected factor for vibration criteria of high sensitive equipment.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.86-93
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• 2017

In this paper, we propose a novel defect detection method using component tree representations of scanning electron microscopy (SEM) images. The component tree contains rich information about the topological structure of images such as the stiffness of intensity changes, area, and volume of the lobes. This information can be used effectively in detecting suspicious defect areas. A quasi-linear algorithm is available for constructing the component tree and computing these attributes. In this paper, we modify the original component tree algorithm to be suitable for our defect detection application. First, we exclude pixels that are near the ground level during the initial stage of component tree construction. Next, we detect significant lobes based on multiple attributes and edge information. Our experiments performed with actual SEM wafer images show promising results. For a $1000{\times}1000$ image, the proposed algorithm performed the whole process in 1.36 seconds.