• 한국재료학회지
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• 제22권9호
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• pp.450-453
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• 2012

In crystalline solar cells, the substrate itself constitutes a large portion of the fabrication cost as it is derived from semiconductor ingots grown in costly high temperature processes. Thinner wafer substrates allow some cost saving as more wafers can be sliced from a given ingot, although technological limitations in slicing or sawing of wafers off an ingot, as well as the physical strength of the sliced wafers, put a lower limit on the substrate thickness. Complementary to these economical and techno-physical points of view, a device operation point of view of the substrate thickness would be useful. With this in mind, BC-BJ Si and GaAs solar cells are compared one to one by means of the Medici device simulation, with a particular emphasis on the substrate thickness. Under ideal conditions of 0.6 ${\mu}m$ photons entering the 10 ${\mu}m$-wide BC-BJ solar cells at the normal incident angle (${\theta}=90^{\circ}$), GaAs is about 2.3 times more efficient than Si in terms of peak cell power output: 42.3 $mW{\cdot}cm^{-2}$ vs. 18.2 $mW{\cdot}cm^{-2}$. This strong performance of GaAs, though only under ideal conditions, gives a strong indication that this material could stand competitively against Si, despite its known high material and process costs. Within the limitation of the minority carrier recombination lifetime value of $5{\times}10^{-5}$ sec used in the device simulation, the solar cell power is known to be only weakly dependent on the substrate thickness, particularly under about 100 ${\mu}m$, for both Si and GaAs. Though the optimum substrate thickness is about 100 ${\mu}m$ or less, the reduction in the power output is less than 10% from the peak values even when the substrate thickness is increased to 190 ${\mu}m$. Thus, for crystalline Si and GaAs with a relatively long recombination lifetime, extra efforts to be spent on thinning the substrate should be weighed against the expected actual gain in the solar cell output power.

• 한국산학기술학회논문지
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• 제13권1호
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• pp.329-332
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• 2012

LED는 저 전력, 긴 수명, 고 휘도, 빠른 응답, 친환경적인 특성의 여러 장점을 갖고 있기 때문에 청색과 녹색 LED는 교통신호, 옥외 디스플레이, 백색 LED는 LCD 후면광 등의 응용 제품에 사용되고 있다. 여기서 LED의 성능을 향상하기 위하여 출력전력과 소자의 신뢰성을 높이고, 동작전압을 낮추어야 LED 칩의 고효율화가 이루어져야 하는데, 이는 에피택셜층, 표면요철, 패턴이 있는 사파이어 기판, 칩 설계의 최적화, 특수 공정의 개선 등의 기술이 우수해야 한다. 본 연구에서는 측면 에칭 기술과 절연층 삽입기술을 이용하여 사파이어 에피 웨이퍼 위에 GaN-기반 백색 LED 칩을 제작하여 그 성능을 조사하였다. LED 칩의 성능을 개선하기 위한 최적화 설계와 CBL(current blocking layer) 삽입 기술의 개선된 공정을 통하여 LED 칩 성능의 향상을 확인할 수 있었으며, 출력 전력은 광 출력 7cd, 순방향 인가전압 3.2V의 값을 얻었다. 현재의 LCD 후면광원으로 사용되고 있는 LED 칩의 출력에 비하여 성능이 개선되었으며, 의료기기 및 LCD LED TV의 후면광원으로 사용할 수 있을 것으로 기대된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.174-174
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• 2008

Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with a metal/ferroelectric/semiconductor gate stack (MFS-FETs) make non-destructive read operation possible. In addition, they also have features such as high switching speed, non-volatility, radiation tolerance, and high density. However, the interface reaction between ferroelectric materials and Si substrates, i.e. generation of mobile ions and short retention, make it difficult to obtain a good ferroelectric/Si interface in an MFS-FET's gate. To overcome these difficulties, Fe-FETs with a metal/ferroelectric/insulator/semiconductor gate stack (MFIS-FETs) have been proposed, where insulator as a buffer layer is inserted between ferroelectric materials and Si substrates. We prepared $SrBi_2Ta_2O_9$ (SBT) film as a ferroelectric layer and $LaZrO_x$ (LZO) film as a buffer layer on p-type (100) silicon wafer for making the MFIS-FET devices. For definition of source and drain region, phosphosilicate glass (PSG) thin film was used as a doping source of phosphorus (P). Ultimately, the n-channel ferroelectric-gate FET using the SBT/LZO/Si Structure is fabricated. To examine the ferroelectric effect of the fabricated Fe-FETs, drain current ($I_d$) versus gate voltage ($V_g$) characteristics in logarithmic scale was measured. Also, drain current ($I_d$) versus drain voltage ($V_d$) characteristics of the fabricated SBT/LZO/Si MFIS-FETs was measured according to the gate voltage variation.

• E2M - 전기 전자와 첨단 소재
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• 제9권1호
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• pp.30-37
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• 1996

Previously, crystallization of a-Si:H films on glass substrates were limited to anneal temperature below 600.deg. C, over 10 hours to avoid glass shrinkage. Our study indicates that the crystallization is strongly influenced by anneal temperature and weakly affected by anneal duration time. Because of the high temperature process and nonconducting substrate requirements for poly-Si TFTs, the employed substrates were limited to quartz, sapphire, and oxidized Si wafer. We report on poly-Si TFT's using high temperature anneal on a Si:H/Mo structures. The metal Mo substrate was stable enough to allow 1000.deg. C anneal. A novel TFT fabrication was achieved by using part of the Mo substrate as drain and source ohmic contact electrode. The as-grown a-Si:H TFT was compared to anneal treated poly-Si TFT'S. Defect induced trap states of TFT's were examined using the thermally stimulated current (TSC) method. In some case, the poly-Si grain boundaries were passivated by hydrogen. A-SI:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly -Si films were achieved by various anneal techniques; isothermal, RTA, and excimer laser anneal. The TFT on as grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from 200 to >$1000^{\circ}C$ The TFT on poly-Si showed an improved $I_on$$I_off$ ratio of $10_6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly Si TFTs.