• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1047-1053
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• 2011

In this paper, we proposed an HF-band wireless power transfer system with adaptive frequency control circuit for efficiency enhancement in a short range. In general, a wireless power transfer system shows an impedance mismatching due to a reflected impedance, because a coupling coefficient is varied with respect to separation distance between two resonating loop antennas. The proposed method can compensate this impedance mismatching by varying input frequency of a voltage-controlled oscillator adaptively with respect to separation distance. Therefore, transmission efficiency is enhanced in a short distance, where large impedance mismatch occurs. The adaptive frequency circuit consists of a directional coupler, a detector, and a loop filter. In order to demonstrate the performance of the proposed system, a wireless power transfer system with adaptive frequency control circuits is designed and implemented, which has a pair of loop antennas with a dimension of 30${\times}$30 $cm^2$. From measured results, the proposed system shows enhanced efficiency performance than the case without adaptive frequency control.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.77-86
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• 2016

This paper describes a dual-mode reference-less CDR(Clock Data Recovery) operating at full / half-rate and its operation algorithm. Proposed reference-less CDR consists of a frequency detector, a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a digital block. The frequency and phase detectors operate at both full / half-rate for dual-mode operation and especially the frequency detector is capable of detecting the difference between data rate and clock frequency in the dead zone of general frequency detectors. Dual-mode reference-less CDR with the proposed algorithm can recover the data and clock within 1.2-1.3 us and operates reliably at both full-rate (2.7 Gb/s) and half-rate (5.4 Gb/s) with 0.5-UI input jitter.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.11
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• pp.56-60
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• 2009

In this paper, a novel voltage controlled oscillator (VCO) has been presented by using the microstrip square multiple spiral resonator for reducing the phase noise of VCO. The microstrip multiple square resonator has the large coupling coefficient value, which makes a high Q value, and has reduced phase noise of VCO. The VCO with 1.8 V power supply has phase noise of -115.0~-117.34 dBc/Hz @100 kHz in the tuning range, 8.935~9.4 GHz. When it has been compared with microstrip square multiple spiral resonator and coventional spiral resonator, the reduced Q value has been -32.7 dB and -57.6 dB respectively. This low phase noise VCO could ve available to a VCO in X-band.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.130-134
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• 2008

This paper presents a clock and data recovery(CDR) using a quarter-rate technique. The proposed CDR helps reduce the VCO frequency and is thus advantageous for high speed application. It can achieve a low jitter operation and extend the pull-in range without a reference clock. The CDR consists of a quarter-rate bang-bang type phase detector(PD) quarter-rate frequency detector(QRFD), two charge pumps circuits(CPs), low pass filter(LPF) and a ring voltage controlled oscillator(VCO). The Proposed CDR has been fabricated in a standard $0.18{\mu}m$ 1P6M CMOS technology. It occupies an active area $1{\times}1mm^2$ and consumes 98 mW from a single 1.8 V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.8
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• pp.964-969
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• 2007

A regulated low phase noise differential colpitts VCO(Voltage Controlled Oscillator) for mobile RFID system is presented. The differential colpitts VCO meets the dense reader environment specifications. The VCO use a $0.35{\mu}m$ technology and achieves tuning range $1.55{sim}2.053 GHz$. Measuring 910 MHz frequency divider output, phase noise performance is -106 dBcMz and -135dBc/Hz at 40 kHz and 1MHz offset, respectively. 5-bit digital coarse-tuning and accumulation type MOS varactors allow for 28.2% tuning range, which is required to cover the LO frequency range of a UHF Mobile RFID system, Optimum design techniques ensure low VCO gain(<45 MHz/V) for good interoperability with the frequency synthesizer. To the author' knowledge, this differential colpitts VCO achieves a figure of merit(FOM) of 1.93dB at 2-GHz band.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.46-54
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• 1984

A silicon-gate n-well CMOS process with 3 $\mu$m gate length was developed and its possibility for the applications was discussed,. Threshold voltage was easily controlled by ion implantation and 3-$\mu$m gate length with 650 $\AA$ oxide shows ignorable short channel effect. Large value of Al-n+ contact resistance is one of the problems in fabrications of VLSI circuits. Transfer characteristics of CMOS inverter is fairly good and the propagation delay time per stage in ring oscillator with layout of (W/L) PMOS /(W/L) NMOS =(10/5)/(5/5) is about 3.4 nsec. catch-up occurs on substrate current of 3-5 mA in this process and critically dependent on the well doping density and nt-source to n-well space. Therefore, research, more on latch-up characteristics as a function of n-well profile and design rule, especially n+-source to n-well space, is required.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.4
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• pp.247-252
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• 2009

This paper presents an Integer-N phase-locked loop (PLL) frequency synthesizer using a novel prescaler based on a charge pump and clock triggering circuit. A quadrature VCO has been designed for the 900MHz UHF RFID application. In this circuit, a voltage-controlled oscillator(VCO), a novel Prescaler, phase frequency detector(PFD), charge pump(CP), and analog lock detector(ALD) have been integrated with 0.35-${\mu}m$CMOS process. The integer divider has been developed with a verilog-HDL module, and the PLL mixed mode simulation has been performed with Spectre-Verilog co-simulator. The sweep range of VCO is designed from 828 to 960 MHz and the VCO generates four phase quadrature signals. The simulation results show that the phase noise of VCO is -102dBc/Hz at 100 KHz offset frequency, and the maximum lock-in time is about 4us with 32MHz step change (from 896 to 928 MHz).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.7
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• pp.1652-1656
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• 2014

In this work, we demonstrated a 77 GHz waveguide VCO with transition from WR-12 to WR-10 for anti-collision radar applications. The fabricated waveguide VCO consists of a GaAs-based Gunn diode, a varactor diode, a waveguide transition, and two bias posts for operating as a LPF and a resonator. The cavity is designed for fundamental mode at 38.5 GHz and operated at second hormonic of 77 GHz. The waveguide transition has a 1.86 dB of insertion loss and -30.22 dB of S11 at the center frequency of 77 GHz. The fabricated VCO achieves an oscillation bandwidth of 870 MHz. Output power is from 12.0 to 13.75 dBm and phase noise is -100.78 dBc/Hz at 1 MHz offset frequency from the carrier.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.12
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• pp.22-27
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• 2007

In this paper, a novel voltage-controlled oscillator (VCO) using the microstrip square open loop split ring resonator (OLSRR) is presented for reducing the phase noise. For this purpose, the square-shaped split ring resonator (SRR) haying the form of the microstrip square open loop is investigated. Compared with the microstrip square open loop resonator, the microstrip square OLSRR has the larger coupling coefficient value, which makes a higher Q value, and has reduced the phase noise of VCO. The VCO with 1.7V power supply has the phase noise of $-120\sim-116.5$ dBc/Hz @ 100 kHz in the tuning range, $5.746\sim5.854$ GHz. The figure of merit (FOM) of this VCO is $-200.33\sim-197$ dBc/Hz @ 100 kHz in the same tuning range.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1A
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• pp.134-141
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• 2007

This paper presents a frequency synthesizer(FS) for 5.2GHz/2.4GHz dual band wireless applications which is designed in a standard $0.18{\mu}m$ CMOS1P6M process. The 2.4GHz frequency is obtained from the 5.2GHz output frequency of Voltage Controlled Oscillator (VCO) by using the Switched Capacitor (SC) and the divider-by-2. Power dissipations of the proposed FS and VCO are 25mW and 3.6mW, respectively. The tuning range of VCO is 700MHz and the locking time is $4{\mu}s$. The simulated phase noise of PLL is -101.36dBc/Hz at 200kHz offset frequency from 5.0GHz with SCA circuit on.