• 조명전기설비학회논문지
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• 제19권7호
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• pp.113-121
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• 2005

본 논문에서는 오존발생장치의 전원측 파형에 포함되는 고주파수의 노이즈를 제거하고, 디지털 궤환 제어에 의해 오존 출력을 제어하기 위하여 전원장치의 출력측 LC 필터와 방전관 용량으로부터 커패시터 전압과 전류를 검출하여 2중의 제어루프를 설계하였다. 디지털 제어기의 연산지연시간을 보상하기 위하여 연산지연시간을 전원장치 플랜트의 고유한 파라미터로 가정하고, 플랜트 모델에 포함시켜 모델링 하였다. 오존발생장치의 부하변동에 따르는 과도상태 응답특성을 개선하고, 파라미터 변동에 강인한 특성을 얻기 위하여 내부 전류 모델 제어기를 제안하였다. 또한 오존발생장치용 전원장치에서 영 오차의 정상 상태를 얻기 위하여 외부 전압 제어루프를 구성하여 비례 제어기와 공진 제어기를 병렬로 연결한 비례-공진 전압제어기를 제안하였다.

• Journal of Power Electronics
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• 제19권4호
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• pp.881-893
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• 2019

This paper proposes a practical sliding-mode controller design for shaping the impedances of cascaded boost-converter power decoupling circuits for reducing the second order harmonic ripple in photovoltaic (PV) current. The cascaded double-boost converter, when used as power decoupling circuit, has some advantages in terms of a high step-up voltage-ratio, a small number of switches and a better efficiency when compared to conventional topologies. From these features, it can be seen that this topology is suitable for residential (PV) rooftop systems. However, a robust controller design capable of rejecting double frequency inverter ripple from passing to the (PV) source is a challenge. The design constraints are related to the principle of the impedance-shaping technique to maximize the output impedance of the input-side boost converter, to block the double frequency PV current ripple component, and to prevent it from passing to the source without degrading the system dynamic responses. The design has a small recovery time in the presence of transients with a low overshoot or undershoot. Moreover, the proposed controller ensures that the ripple component swings freely within a voltage-gap between the (PV) and the DC-link voltages by the small capacitance of the auxiliary DC-link for electrolytic-capacitor elimination. The second boost controls the main DC-link voltage tightly within a satisfactory ripple range. The inverter controller performs maximum power point tracking (MPPT) for the input voltage source using ripple correlation control (RCC). The robustness of the proposed control was verified by varying system parameters under different load conditions. Finally, the proposed controller was verified by simulation and experimental results.

• Journal of Electrical Engineering and Technology
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• 제7권5호
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• pp.664-671
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• 2012

This paper presents the application of Unified Power Flow Controller (UPFC) in order to simultaneous control of power flow and voltage and also damping of Low Frequency Oscillations (LFO) at a Single-Machine Infinite-Bus (SMIB) power system installed with UPFC. PI type controllers are commonly used controllers for UPFC control. But for the sake of some drawbacks of PI type controllers, the scope for finding a better control scheme still remains. In this regard, in this paper the new IP type controllers are considered as UPFC controllers. The parameters of these IP type controllers are tuned using Genetic Algorithms (GA). Also a stabilizer supplementary controller based UPFC is considered for increasing power system damping. To show the ability of IP controllers, this controller is compared with classical PI type controllers. Simulation results emphasis on the better performance of IP controller in comparison with PI controller.

• IEIE Transactions on Smart Processing and Computing
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• 제5권2호
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• pp.71-76
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• 2016

A controller area network (CAN) receiver measures differential voltage on a bus to determine the bus level. Since 3.3V transceivers generate the same differential voltage as 5V transceivers (usually ${\geq}1.5V$), all transceivers on the bus (regardless of supply voltage) can decipher the message. In fact, the other transceivers cannot even determine or show that there is anything different about the differential voltage levels. A new CMOS RC oscillator insensitive supply voltage for clock generation in a CAN transceiver was fabricated and tested to compensate for this drawback in CAN communication. The system consists of a symmetrical circuit for voltage and current switches, two capacitors, two comparators, and an RS flip-flop. The operational principle is similar to a bistable multivibrator but the oscillation frequency can also be controlled via a bias current and reference voltage. The chip test experimental results show that oscillation frequency and power dissipation are 500 kHz and 5.48 mW, respectively at a supply voltage of 3.3 V. The chip, chip area is $0.021mm^2$, is fabricated with $0.18{\mu}m$ CMOS technology from SK hynix.

• 한국정보통신학회논문지
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• 제11권8호
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• pp.1552-1557
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• 2007

본 논문에서는 밴드갭 기준전압을 이용하여 동작온도에 무관한 PWM(Pulse Width Modulation) 제어 회로를 설계 하였다. 동작온도에 무관한 PWM 제어기는 BiCMOS 기술을 이용하여 동작온도에 무관한 기준전압과 동작온도에 따라 변화하는 두개의 기준 전압을 이용하였다. 설계되어진 회로는 공급전압 3.3volt를 사용하였으며, 출력 주파수는 1MHz이다. 회로의 시뮬레이션 결과 동작 온도가 $0^{\circ}C$에서 $70^{\circ}C$까지 변화할 때, PWM 제어기의 출력 펄스폭의 변화는 상온에 비하여 +0.86%에서 -0.38%였다.

• 대한전기학회논문지
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• 제37권6호
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• pp.376-382
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• 1988

A small-signal low-frequency disturbance of the input line affects the regulated-output voltage of the series resonant converter. To mitigate the detrimental effect, the output feedback PI-controller is employed. Small-signal linear models are represented to characterize the closed loop series resonant converter system. Design equations for the PI-controller which satisfy stability and percent ripple conditions are derived from the closed-loop linear model. Experimental results are presented which show excellent correlation with theory.

• 전력전자학회논문지
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• 제27권6호
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• pp.498-506
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• 2022

This study proposes a design methodology for bidirectional, series-resonant, dual-active bridge (SRDAB) converters. The circuit parameters of the SRDAB converters are designed by considering the output power and efficiency of the converter. The proposed method can be used to design a high-power, high-efficiency SRDAB converter. A voltage controller is employed to manipulate the output voltage of the converter, and the controller gains are selected using the transfer function and frequency response of the controller. Simulation results show that the output power of the designed SRDAB converter is 2 kW per converter module as designed. In addition, the performance of the voltage controller is evaluated using the simulation and experimental results. The output voltage follows the reference voltage within 10 ms under the step change of the reference command. The output voltage also follows the reference voltage under the step load change. The efficiency of the designed SRDAB converter is 95.6%.

• 대한전자공학회논문지SD
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• 제47권5호
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• pp.71-79
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• 2010

본 논문은 LLC 공진 제어 IC(Integrated Circuit) 설계에 관한 것이다. LLC 공진 제어 IC는 DC/DC 변환하기 위해서 외부의 공진 회로에 입력되는 주파수를 조정하여 트랜스포머를 통해서 2차 측의 출력 전압을 조정한다. 공진회로에 펄스를 공급하기 위한 클럭 생성기가 내장되어 있고, 클럭 주파수는 외부 저항을 사용하여 튜닝이 가능하다. 또한 외부 피드백 입력되는 전압을 이용해 주파수 조정이 가능하도록 VCO(Voltage Controlled Oscillator) 기능을 내장하였다. 동작의 신뢰성을 높이고 회로를 보호하기 위해서 UVLO(Under Voltage Lock Out), brown out, fault detector의 보호회로를 내장하였고, 입력 커패시턴스가 큰 용량의 IGBT(Insulated Gate Bipolar Transistor)를 구동하기 위해서 높은 전압, 전류의 제공이 가능한 HVG(High Side Driver), LVG(Low Side Driver) 드라이버 회로를 내장하였다. LLC 공진 제어 회로를 하나의 칩으로 구현하여 LLC 공진 회로를 제어하는데 있어 필요한 회로들을 설계하였다. 설계한 LLC 공진 제어 IC는 0.35 um 2P3M BCD 공정으로 제작하였다. 칩의 면적은 $1400um{\times}1450um$ 이고, 5V, 15V 두 가지의 전원 전압을 사용한다.

• Journal of Power Electronics
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• 제12권2호
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• pp.344-356
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• 2012

In recent years, multilevel technology has become an effective and practical solution in the field of moderate and high voltage applications. This paper discusses an APF with a three-level NPC inverter. Obviously, the application of such converter to APFs is hindered by the problem of the voltage unbalance of DC capacitors, which leads to system instability. This paper comprehensively analyzes the theoretical limitations of the neutral-point voltage balancing problem for tracking different harmonic currents utilizing current switching functions from the space vector PWM (SVPWM) point of view. The fluctuation of the neutral point caused by the load currents of certain order harmonic frequency is reported and quantified. Furthermore, this paper presents a close-loop digital control algorithm of the DC voltage for this APF. A PI controller regulates the DC voltage in the outer-loop controller. In the current-loop controller, this paper proposes a simple neutral-point voltage control method. The neutral-point voltage imbalance is restrained by selecting small vectors that will move the neutral-point voltage in the direction opposite the direction of the unbalance. The experiment results illustrate that the performance of the proposed approach is satisfactory.

• 한국조명전기설비학회지:조명전기설비
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• 제7권3호
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• pp.27-33
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• 1993

본 논문은 캐리어 주파수 20kHz 이상의 고주파 전압형 PWM 인버터를 구동하기 위한 디지털 제어기에 관한 연구이다.적절한 PWM 패턴을 선택하기 위하여 기존의 PWM을 분석하였고, 비동기형 계단 정현파를 기준신호로 하여 제어기의 PWM 패턴을 구하였으며, PWM 제어방법은 가변 캐리어 비를 이용하였다.PWM 제어기는 모두 디지털 방식으로 구성하였다. 특히, 제시된 제어기의 구성은 연산 및 데이터 처리와 PWM 패턴 합성을 8비트 원칩 마이크로프로세서와 디지털 로직으로 나누어 설계하므로써 제어에 대한 속응성 및 제어성을 개선하였다. 또 변조도 데이터를 9비트로 출력하도록 프로그램을 적절히 이용하여 데이터 처리능력을 높였다.디지털 제어기는 회로구성을 i8051과 원칩 EPLD로 구성하였고, 설계된 제어기는 전압형 인버터를 동작시켜 제어성을 고찰하였다. 그리고 전압형 인버터 시스템의 고조파와 전류파형을 평가 분석하였다.