• Proceedings of the Materials Research Society of Korea Conference
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• 2007.05a
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• pp.28.2-28.2
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• 2007

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.5.2-5.2
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• 2009

From 10 years ago, the development of nano-devices endeavored to achieve reconstruction of information technology (IT) and nano technology (NT) industry. Among the many materials for the IT and NT industry, zinc oxide (ZnO) is a very promising candidate material for the research of nano-device development. Nano-structures of ZnO-based materials were grown easily via various methods and it attracts huge attention because of their superior electrical and optical properties for optoelectronic devices. Recently, among the various growth methods, MOCVD has attracted considerable attention because it is suitable process with benefits such as large area growth, vertical alignment, and accurate doping for nano-device fabrication. However, ZnO based nanowires grown by MOCVD process were had the principal problems of 1st interfacial layers between substrate and nanowire, 2nd a broad diameter (about 100 nm), and 3rd high density, and 4th critical evaporation temperature of Zinc precursors. In particular, the growth of high performance nanowire for high efficiency nano-devices must be formed at high temperature growth, but zinc precursors were evaporated at high temperature.These problems should be repaired for materialization of ultra high performance quantum devices with quantum effect. For this reason, we firstly proposed the growth method of vertical aligned slim MgZnO nanowires (< 10 nm) without interfacial layers using self-phase separation by introduced Mg at critical evaporation temperature of Zinc precursors ($500^{\circ}C$). Here, the self-phase separation was reported that MgO-rich and the ZnO-rich phases were spontaneously formed by additionally introduced Mg precursors. In the growth of nanowires, the nanowires were only grown on the wurzite single crystal seeds as ZnO-rich phases with relatively low Mg composition (~36 at %). In this study, we investigated the microstructural behaviors of self-phase separation with increasing the Mg fluxes in the growth of MZO NWs, in order to secure drastic control engineering of density,diameter, and shape of nanowires.

• Journal of the Korean Ceramic Society
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• v.47 no.6
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• pp.623-626
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• 2010

We synthesized ZnO nanowires patterned on Si substrate and investigated the field emission properties of the nanowires. Firstly, Au catalyst layers were fabricated on Si substrate by photo-lithography and lift-off process. The diameter of Au pattern was $50\;{\mu}m$ and the pattern was arrayed as $4{\times}4$. ZnO nanowires were grown on the Au catalyst pattern by the aid of Au liquid phase. The orientation of the ZnO nanowires was vertical on the whole. Sufficient brightness was obtained when the electric field was $5.4\;V/{\mu}m$ and the emission current was $5\;mA/cm^2$. The threshold electric field was $5.4\;V/{\mu}m$ in the $4{\times}4$ array of ZnO nanowires, which is quite lower than that of the nanowires grown on the flat Si substrate. The lower threshold electric field of the patterned ZnO nanowires could be attributed to their vertical orientation of the ZnO nanowires.

• Proceeding of EDISON Challenge
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• 2017.03a
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• pp.398-403
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• 2017

본 연구에서는 gate-all-around(GAA) 수직 나노선 Field-Effect Transistor(FET)의 소스/드레인 반도체/실리사이드 접합에 존재하는 Schottky 장벽이 트랜지스터의 DC특성에 미치는 영향에 대하여 조사하였다. Non-Equilibrium Green's Function와 Poisson 방정식 기반의 시뮬레이터를 사용하여, Schottky 장벽의 위치와 높이, 그리고 채널 단면적의 크기에 따른 전류-전압 특성 곡선과 에너지 밴드 다이어그램을 통해 분석을 수행하였다. 그 결과, 드레인 단의 Schottky 장벽은 드레인 전압에 의해 장벽의 높이가 낮아져 전류에 주는 영향이 작지만, 소스 단의 Schottky 장벽은 드레인 전압과 게이트 전압으로 제어가 불가능하여 외부에서 소스 단으로 들어오는 캐리어의 이동을 방해하여 큰 DC성능 저하를 일으킨다. 채널 단면적 크기에 따른 DC특성 분석 결과로는 동작상태의 전류밀도는 채널의 폭이 5 nm 일 때까지는 유지되고, 2 nm가 되면 그 크기가 매우 작아지지만, 채널 단면적은 Schottky 장벽에 영향을 끼치지 못하였다. 본 논문의 분석 결과로 향후 7 nm technology node 에 적용될 GAA 수직 나노선 FET의 소자 구조 설계에 도움이 되고자 한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.814-817
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• 2010

AAO thin films prepared by a two-step anodization process have pores that are uniform in diameter, highly ordered, and perfectly vertical with respect to the plane of the nano template. Further, the pore size and interpore distance can be easily controlled by varying the anodizing voltage and acid electrolyte. When metals are electrochemically deposited in the pores, metal nanowires that are highly ordered and uniform in diameter are formed in each pore.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.418-418
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• 2008

The electrochemical etching of silicon in HF-based solutions is known to form various types of porous structures. Porous structures are generally classified into three categories according to pore sizes: micropore (below 2 nm in size), mesopore (2 ~ 50 nm), and macropore (above 50 nm). Recently, the formation of macropores has attracted increasing interest because of their promising characteristics for an wide scope of applications such as microelectromechanical systems (MEMS), chemical sensors, biotechnology, photonic crystals, and photovoltaic application. One of the promising applications of macropores is in the field of MEMS. Anisotropic etching is essential step for fabrication of MEMS. Conventional wet etching has advantages such as low processing cost and high throughput, but it is unsuitable to fabricate high-aspect-ratio structures with vertical sidewalls due to its inherent etching characteristics along certain crystal orientations. Reactive ion dry etching is another technique of anisotropic etching. This has excellent ability to fabricate high-aspect-ratio structures with vertical sidewalls and high accuracy. However, its high processing cost is one of the bottlenecks for widely successful commercialization of MEMS. In contrast, by using electrochemical etching method together with pre-patterning by lithographic step, regular macropore arrays with very high-aspect-ratio up to 250 can be obtained. The formed macropores have very smooth surface and side, unlike deep reactive ion etching where surfaces are damaged and wavy. Especially, to make vertical microwire or nanowire arrays (aspect ratio = over 1:100) on silicon wafer with top-down photolithography, it is very difficult to fabricate them with conventional dry etching. The electrochemical etching is the most proper candidate to do it. The pillar structures are demonstrated for n-type silicon and the formation mechanism is well explained, while such a experimental results are few for p-type silicon. In this report, In order to understand the roles played by the kinds of etching solution and mask patterns in the formation of microwire arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, dimethyl sulfoxide (DMSO), iso-propanol, and mixtures of HF with water on the structure formation on monocrystalline p-type silicon with a resistivity with 10 ~ 20 $\Omega{\cdot}cm$. The different morphological results are presented according to mask patterns and etching solutions.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.88.1-88.1
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• 2012

Silicon nanowires (SiNWs), due to their unusual quantum-confinement effects that lead to superior electrical and optical properties compared to those of the bulk silicon, have been widely researched as a potential building block in a variety of novel electronic devices. The conventional means for the synthesis of SiNWs has been the vapor-liquid-solid method using chemical vapor deposition; however, this method is time consuming, environmentally unfriendly, and do not support vertical growth. As an alternate, the electroless etching method has been proposed, which uses metal catalysts contained in aqueous hydrofluoric acids (HF) for vertically etching the bulk silicon substrate. This new method can support large-area growth in a short time, and vertically aligned SiNWs with high aspect ratio can be readily synthesized with excellent reproducibility. Nonetheless, there still are rooms for improvement such as the poor surface characteristics that lead to degradation in electrical performance, and non-uniformity of the diameter and shapes of the synthesized SiNWs. Here, we report a facile method of SiNWs synthesis having uniform sizes, diameters, and shapes, which may be other than just cylindrical shapes using a modified nanosphere lithography technique. The diameters of the polystyrene nanospheres can be adjustable through varying the time of O2 plasma treatment, which serve as a mask template for metal deposition on a silicon substrate. After the removal of the nanospheres, SiNWs having the exact same shape as the mask are synthesized using wet etching technique in a solution of HF, hydrogen peroxide, and deionized water. Different electrical and optical characteristics were obtained according to the shapes and sizes of the SiNWs, which implies that they can serve specific purposes according to their types.