• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.425-435
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• 2016

This paper describes a spread-spectrum clock generation method by utilizing a ${\Delta}{\Sigma}$ digital PLL (DPLL) which is solely based on binary phase detection and does not require a linear time-to-digital converter (TDC) or other linear digital-to-time converter (DTC) circuitry. A 1-bit high-order ${\Delta}{\Sigma}$ modulator and a hybrid finite-impulse response (FIR) filter are employed to mitigate the phase-folding problem caused by the nonlinearity of the bang-bang phase detector (BBPD). The ${\Delta}{\Sigma}$ DPLL employs a two-point modulation technique to further enhance linearity at the turning point of a triangular modulation profile. We also show that the two-point modulation is useful for the BBPLL to improve the spread-spectrum performance by suppressing the frequency deviation at the input of the BBPD, thus reducing the peak phase deviation. Based on the proposed architecture, a 3.2 GHz spread-spectrum clock generator (SSCG) is implemented in 65 nm CMOS. Experimental results show that the proposed SSCG achieves peak power reductions of 18.5 dB and 11 dB with 10 kHz and 100 kHz resolution bandwidths respectively, consuming 6.34 mW from a 1 V supply.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.11 no.6
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• pp.64-73
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• 1997

RPWM(Random Pulse Width Modulation) techniques have been attracting an interest as an excellent reduction method of acoustic noise on the inverter drive system. Using randomly changed switching fre-quency of the inverter, the power spectrum of the electromagnetic acoustic noise can be spread out into the wide-band area. The wide band noise is much more comfortable and less annoying than the narrow-band one. This paper describes an implementationof the triangular carrier frequency modultde RPWM inverter drive system The poweer soedtrum of the noise emittde from the induction motro was measured in the anechoic chamber. The analysis of the sources for the acoustic noise and the effects of the noise reduction are confirmed by the ceasured dpectra of the noise. Real-time RPWM along with the speed control was achieved by high speed DSP(Digital Signal Processor ) TmS320C31, By changing the center frequency and the bandwidth of the carrier, theis real-time RPWM scheme can be used as an efficient switching frequency band acoustic noise reduction method for the inverter system with variant load conditions.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.887-890
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• 2004

This paper presents a microprocessor controlled electronic ballast for HID lamps, which gives automatic switching between MH and HPS lamps. Lamp identification is carried out by checking variation of lamp impedance at warm-up phase. Direct spread spectrum is done by applying 1 kHz triangular wave for removing acoustic resonance. This frequency modulation of 1 kHz gives also low EMI level. The microprocessor controls the voltage of DC-bus, the voltage of ignition pulses, the power of output. A 250W electronic ballast is implemented with ATmega16 CPU.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2003.11a
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• pp.31-35
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• 2003

This paper presents a microprocessor controlled digital ballast for HID lamps, which gives intelligent features such as a precise power control, optimum ignition voltage and detection of end of life. Average current mode PFC is employed for reducing EMI and a universal input. Direct spread spectrum is done by applying 1 KHz triangular wave for removing acoustic resonance. This frequency modulation of 1 KHz gives also low EMI level and no ripple on lamp current. The microprocessor controls the voltage of DC-bus, the voltage of ignition pulses, the power of output and the bandwidth of spread spectrum. A 250W digital ballast is implemented with an efficiency of 93％ and a maximum EMI level of 55 ㏈${\mu}$V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.10
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• pp.7-13
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• 2010

A compact phase interpolator (PI) based spread spectrum clock generator (SSCG) for electromagnetic interference (EMI) reduction is presented. The proposed SSCG utilizes a digitally controlled phase interpolation technique to achieve triangular frequency modulation with less design complexity and small power and area overhead. The novel SSCG can generate the system clock with a programmable center-spread spectrum range of up to +/- 2 % at 200 MHz, while maintaining the clock duty cycle ratio without distortions. The PI-based SSCG has been designed and evaluated in 0.18-um 1.8-V CMOS technology, which consumes about 5.0 mW at 200MHz and occupies a chip size of $0.092mm^2$ including a DLL.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.498-501
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• 2005

Photonic crystals, periodic structure with a high refractive index contrast modulation, have recently become very interesting platform for manipulation of light. The existence of a photonic bandgap, a frequency range in which propagation of light is prevented in all direction, makes photonic crystal very useful in application where spatial localization of light is required for waveguide, beam splitter, and cavity. But fabrication of 3 dimensional photonic crystal is still difficult process. a concept that has recently attracted a lot of attention is a planar photonic crystal based on a dielectric membrane, suspended in the air, and perforated with 2 dimensional lattice of hole. We show that the polymer slabs suspended in air with triangular lattice of air hole can exhibit the in-plane photonic bandgap for TE-like modes. The fabrication of Si master with pillar structure using hot embossing process was investigated for 2 dimensional low-index-contrast photonic crystal waveguide.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.68-73
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• 2009

This paper describes design and implementation of a spread spectrum clock generator (SSCG) for the DisplayPort. The proposed architecture generates the spread spectrum clock using a sigma-delta fractional-N PLL. The SSCG uses a digital End order MASH 1-1 sigma-delta modulator and a 9bit Up/Dn counter. By using MASH 1-1 sigma-delta modulator, complexity of circuit and chip area can be reduced. The advantage of sigma-delta modulator is the better control over modulation frequency and spread ratio. The SSCG generates dual clock rates which are 270MHz and 162MHz with 0.25% down-spreading and triangular waveform frequency modulation of 33kHz. The peak power reduction is 11.1dBm at 270MHz. The circuit has been designed and fabricated using in 0.18$\mu$m CMOS technology. The chip occupies 0.620mm$\times$0.780mm. The measurement results show that the fabricated chip satisfies the DispalyPort standard.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.9
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• pp.865-871
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• 2016

This work presents a radar signal interferer to be used for evaluating the mutual interference among automotive radars. The developed interfering signal generator is composed of a reference signal generator and a 77 GHz transmitter. Reference signal generator is made up of commercial chips and board, it can generate various modulated signal such as triangular wave, sawtooth wave and random frequency hopping. The transmitter generates 77 GHz band signal by multiplying modulated reference signal frequency 28 times. Transmitter was fabricated using 65 nm CMOS process, it can operate horn antenna by built in on-chip waveguide feeder. The transmitter exhibited 7.31~8.06 dBm output power over a frequency lock range of 75.6~77 GHz.