• 대한전자공학회논문지
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• 제26권9호
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• pp.1359-1368
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• 1989

In this paper, the composite BiCMOS transistor which combines a bipolar transistor and a MOS transistor in a cascade type, is analyzed in terms of I-V characteristics and small signal equivalent circuit. As a result, it has a larger driving capability than MOS transistor and a more extended rante of input voltage than bipolar transistor. Next, a BiCMOS differential amplifier as its application example is designed and compared with the CMOS one and the bipolar one. It increases the driving capability of the CMOS differential amp and improves the linear operation region of the bipolar differential amp.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2002년도 추계학술대회 논문집
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• pp.235-240
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• 2002

In micro-EBM, it is well blown that RC circuit is suitable for discharge circuit because of its low pulse width and relatively high peak current. To increase machining speed without changing unit discharge energy, charge resistance should be decreased. But, if very low, continuous (or normal) arc discharge occurs, then increases electrode wear and reduces machining speed remarkably. In this paper, RC circuit with transistor is used to micro-EDM. Experimental results show that RC circuit with transistor can cut off continuous (or normal) arc discharge effectively if duty factor and switching period of transistor are set up optimally. Through experiments with varying charge resistance, it can be known that RC circuit with transistor has about two times faster machining speed than that of RC circuit. Especially, it has prominent rise-effect of machining speed in low unit discharge energy, so that a high-quality and high-speed micro-EDM can be realized through RC circuit with transistor.

• 반도체디스플레이기술학회지
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• 제16권3호
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• pp.59-64
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• 2017

As the demand on displays increases, new thin-film transistors such as metal oxide transistor are continuously being invented. When designing a circuit consisting of such new transistors, a new transistor model based on proper charge transport mechanisms is needed for each of them. In this paper, a modeling framework which enables to choose charge transport mechanisms that are limited to certain operation regions and assemble them into a transistor model instead of making an integrated transistor model dedicated to each transistor. The framework consists of a graphic user interface to choose charge transport models and a current calculation part, which is also implemented in AIM-SPICE for circuit simulation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.163-166
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• 2004

모바일향 90nm DRAM을 개발하기 위하여 비대칭 채널 구조를 갖는 Recess Channel Array Transistor (RCAT)로 cell transistor를 구현하였다. DRAM cell transistor에서 junction leakage current 증가는 DRAM retention time 열화에 심각한 영향을 미치는 요인으로 알려져 있으며, DRAM의 minimum feature size가 점점 감소함에 따라 short channel effect의 영향으로 junction leakage current는 더욱 더 증가하게 된다. 본 실험에서는 short channel effect의 영향에 의한 junction leakage current를 감소시키기 위하여 Recess Channel Array Transistor를 도입하였고, cell transistor의 채널 영역을 비대칭으로 형성하여 data retention time을 증가시켰다. 비대칭 채널 구조을 이용하여 Recess Channel Array Transistor를 구현한 결과, sub-threshold 특성과 문턱전압, Body effect, 그리고, GIDL 특성에는 큰 유의차가 보이지 않았고, I-V특성인 드레인 포화전류(IDS)는 대칭 채널 구조인 transistor 대비 24.8% 정도 증가하였다. 그리고, data retention time은 2배 정도 증가하였다. 본 실험에서 얻은 결과는 향후 저전압 DRAM 개발과 응용에 상당한 기여를 할 것으로 기대된다.

• 한국전자통신학회논문지
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• 제8권1호
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• pp.93-98
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• 2013

본 논문에서는 유기박막트랜지스터용 절연막에 활용코자 플라즈마 중합방법을 이용하여 PMMA 절연막을 제작하였다. 유기트랜지스터 성능향상을 위해 전극구조에 따른 특성을 파악하고자 트랜지스터의 이동도 및 출력특성을 본결과, 상부전극구조의 경우 최대 이동도는 $8{\times}10^{-3}[cm^2V^{-1}s^{-1}]$을 보이고 하부전극구조의 경우 $2{\times}10^{-4}[cm^2V^{-1}s^{-1}]$의 낮은 이동도 값을 얻었으며, 하부전극구조의 경우 off current값이 증가되는 특성을 볼 수 있다. 그러므로 유기트랜지스터의 전극구조는 상부전극 방식이 좋은 것 알 수 있었다.

• 한국전자통신학회논문지
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• 제8권6호
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• pp.797-803
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• 2013

본 논문에서는 플라즈마 중합법에 의해 유기절연막을 제작 후 이를 이용한 유기박막트랜지스터의 특성향상을 위해 반도체박막의 표면처리를 하였다. 그 결과 반도체층의 $O_2$ 플라즈마을 활용하여 30 [sec]동안 표면처리시 박막의 표면에너지는 $38mJ/m^2$값에서 $72mJ/m^2$값으로 증가되었으며, 이에 따른 유기트랜지스터의 이동도는 평균값 기준하여 29% 증가된 $0.057cm^2V^{-1}s^{-1}$의 값으로 증가된 값을 얻을 수 있었다. 이로부터 반도체박막 표면개질에 의한 유기트랜지스터의 이동도 특성향상이 가능함을 알았다.

• 정보처리학회논문지A
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• 제15A권2호
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• pp.69-74
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• 2008

본 논문은 MOS 전류모드 논리회로 (MOS current-mode logic circuit)의 누설전류를 감소시키기 위해 슬립 트랜지스터 (sleep-transistor) 트랜지스터를 이용하여 저 전력 MOS 전류모드 논리회로를 구현하는 새로운 구조를 제안하였다. 슬립 트랜지스터는 누설전류를 최소화하기 위해 고 문턱전압 PMOS 트랜지스터 (high-threshold voltage PMOS transistor)를 사용하였다. $16\;{\times}\;16$ 비트 병렬 곱셈기를 제안한 구조에 적용하여 제안한 구조의 타당성을 입증하였다. 이 회로는 기존 MOS 전류모드 논리회로 구조에 비해 대기전력소모가 1/50으로 감소하였다. 이 회로는 삼성 $0.35\;{\mu}m$ 표준 CMOS 공정을 이용하여 설계하였으며, HSPICE를 이용하여 검증하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.307-309
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• 2009

We have fabricated vertical-type organic transistors (static induction transistors; SITs) with built-in nano-triode arrays formed in parallel by a colloidal-lithography technique. Using this technique, we could fabricate a microstructure in a lateral direction within a large-scale organic device without relying on photolithography. The organic transistor showed low operating voltages, high current output, and large transconductance.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.294.1-294.1
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• 2016

Transition metal dichalcogenides (TMDs) with two-dimensional layered structure, such as molybdenum disulfide (MoS2) and tungsten diselenide (WSe2), are considered attractive materials for future semiconductor devices due to its relatively superior electrical, optical, and mechanical properties. Their excellent scalability down to a monolayer based on the van der Waals layered structure without surface dangling bonds makes semiconductor devices based on TMD free from short channel effect. In comparison to the widely studied transistor based on MoS2, researchs focusing on WSe2 transistor are still limited. WSe2 is more resistant to oxidation in humid ambient condition and relatively air-stable than sulphides such as MoS2. These properties of WSe2 provide potential to fabricate high-performance filed-effect transistor if outstanding electronic characteristics can be achieved by suitable metal contacts and doping phenomenon. Here, we demonstrate the effect of two different metal contacts (titanium and platinum) in field-effect transistor based on WSe2, which regulate electronic characteristics of device by controlling the effective barreier height of the metal-semiconductor junction. Electronic properties of WSe2 transistor were systematically investigated through monitoring of threshold voltage shift, carrier concentration difference, on-current ratio, and field-effect mobility ratio with two different metal contacts. Additionally, performance of transistor based on WSe2 is further enhanced through reliable and controllable n-type doping method of WSe2 by triphenylphosphine (PPh3), which activates the doping phenomenon by thermal annealing process and adjust the doping level by controlling the doping concentration of PPh3. The doping level is controlled in the non-degenerate regime, where performance parameters of PPh3 doped WSe2 transistor can be optimized.

• 대한전자공학회논문지
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• 제26권8호
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• pp.1290-1298
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• 1989

A new dynamic RAM cell called Trench Epitaxial Transistor Cell (TETC) has been developed for 4M to 16M DRAMS. Also the fabrication process for device isolation which can decrease the narrow effect using SEG process has been developed. We verified the characteristic of the new cell structure with the PICSES simulator on VAX8450.