• Journal of the Korean Wood Science and Technology
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• v.52 no.3
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• pp.276-288
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• 2024

This study was conducted to reproduce the woodworking process of Baekje wooden storage facilities. Green timber of Quercus spp. was processed using ancient woodworking tools, and the tool-trace formed in this process were compared with the tool-trace of actual excavated artifacts. In the tool-trace analysis, the length and shape of the tool-trace were objectively recorded using a 3D Scan, and that were difficult to confirm with photograph were confirmed through stereoscopic microscope. As a result, there were two types of adze's tool-trace. One of them is minute straight Blade-top trace line when trimming the wood surface and the other is Plucked trace that appear when strongly chop at the wood. When a chisel bat was not used, a long and wide continuous shape blade trace was produced. And when the chisel head was struck with the chisel bat, a straight blade-top trace was regularly observed. Saw-trace was identified in several layers with fine straight stripes. Through this, it was found that the tool-trace of the woodworking tools, which is estimated to have been used in each process, and the tool-trace remaining in the Baekje wooden storage facility coincide.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.24-31
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• 1998

This paper presents a pipeline high-level synthesis tool for designing trace-back systolic array viterbi decoder. It consists of a dta flow graph(DFG) generator and a pipeline data path synthesis tool. First, the DFG of the vitrebi decoder is generated in the from of VHDL netlist. The inputs to the DFG generator are parameters of the convolution encoder. Next, the pipeline scheduling and allocationare performed. The synthesis tool explores the design space efficiently, synthesizes various designs which meet the given constraints, and choose the best one.

• The KIPS Transactions:PartA
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• v.12A no.1 s.91
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• pp.1-6
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• 2005

This paper presents a new algorithm on low power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. And the spurious switching activity of the trace-back unit is reduced by making use of a clock gating method. Using the SYNOPSYS power estimation tool, DesignPower, our experimental result shows the average $40{\%}$ power reduction and $23{\%}$ area increase against the trace-back unit introduced in [1].

• Journal of the Korea Furniture Society
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• v.26 no.1
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• pp.51-60
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• 2015

Interior designer Sugimoto Takashi uses salvaged material and natural thing for aesthetical purpose. These material performs not just as fun stuff but as design tool in order to set up cultural meaning which modern society always lacks for. The method of communicating the meaning is the multi-layered trace on them. There are three types of trace. They are harsh texture of surface, untrimmed outline, and gathering & arrangement. Through these formation methods of trace, Sugimoto can suggest various curtural meanings such as vanishing value of old-fashioned lifestyle, primitive energy of nature, and sincere touch of somebody. As a result, the trace in Sugimoto's design is an endeavor to exist tradition(the long ago) and nature(the far away) in here-and-now interior space.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.7
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• pp.203-209
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• 1999

In this paper, we present the methods to predict the milled surface shapes in profile milling process. In the cutting process, tools are deflected due to the cutting forces varying with the imposed depth of cut and feedrate. Thus, the final shapes of the milled surface, generated by the nominal tool trajectory, are different from the required profile. In order to predict the milled surface shapes, we present two methods based on: (1) the deflected tool profile and (2) the trace of contact point between the tool and the workpiece. In the first method, we make an assumption that the milled surface corresponds to the deflected tool profile. In another method, we make we make an assumption that the milled surface is generated by the trace of the contact point between the cutting edge of the tool and workpiece. We present the surface generation process by calculating the trajectory of the contact points on the workpiece. Several simulations and experiments are performed to verify the proposed milled surface prediction methods.

• Journal of The Korean Association of Information Education
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• v.2 no.2
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• pp.245-251
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• 1998

This paper designs RDL/PAL interface and performance monitoring tool with providing the Event Expressions. RDL/PAL suggests interface of instrumentation layer and performance analysis layer so that it can extract event data from various trace formats. Also, the Event Expressions is similar to the normal program language, which make possible to obtain result of performance analysis. The programmer can analyze performance regardless of trace format by using the performance monitoring tool which has so much merits.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.78-83
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• 2023

This paper proposes a lightweight trace-driven Processing-In-Memory (PIM) simulator, TP-Sim. TP-Sim is a General Purpose PIM (GP-PIM) simulator that evaluates various PIM system performance-related metrics. Based on instruction and memory traces extracted from the Intel Pin tool, TP-Sim can replay trace files for multiple models of PIM architectures to compare its performance. To verify the availability of TP-Sim, we estimated three different system configurations on the STREAM benchmark. Compared to the traditional Host CPU-only systems with conventional memory hierarchy, simple GP-PIM architecture achieved better performance; even the Host CPU has the same number of in-order cores. For further study, we also extend TP-Sim as a part of a heterogeneous system simulator that contains CPU, GPGPU, and PIM as its primary and co-processors.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.5
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• pp.191-196
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• 2016

Recently, power dissipation is a very significant issue not only in embedded systems and mobile devices but also in high-end modern processors. Especially, by the prevalent use of smart phones and tablet PCs, low power consumption of microprocessors is requisite. In this paper, a fast power measurement tool for a high performance microprocessor based on the trace-driven simulator has been developed. The power model of the microprocessor consists of complex combinational circuits, array structures, and CAM structures. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed to estimate the average power dissipation of each program.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2001.10a
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• pp.14-18
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• 2001

Rise in cutting force causes tool damage and worsens product quality resulting in machining accuracy deterioration. Especially, fragile material cutting brings about breakage of material and worsens product surface quality. In this study, we trace the locus of cutting force and examine the machined surface corresponding to the cutting force loci. and build up a monitoring system for deciding normal operation or not of cutting process.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.514-516
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• 2011

최근 지식 정보화 사회에 있어서 컴퓨터 네트워크 개방화와 함께 컴퓨터 시스템의 보안 위협이 급증하였다. 또한 기본적으로 데이터 보호에 초점을 맞추고 있기 때문에 접근에 대한 제한이 없으며 응용 프로그램에 따라 보안 운영방식이 다르다는 취약점을 가지고 있다. 본 논문은 하드웨어 기반 보안상태 모니터링 가시화를 위하여 TCG에서 제안한 TPM 칩을 기반으로 동작하는 컴퓨팅 환경의 신뢰 상태 및 시스템 자원에 대한 상태 정보를 실시간으로 모니터링하고 분기 추적 모니터링을 통해 논리적 에러의 초기위치를 파악하여 가시화한다.