• Progress in Superconductivity and Cryogenics
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• v.20 no.3
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• pp.21-27
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• 2018

It is difficult to fabricate and maintain moving parts of expander at cryogenic temperature. This paper describes numerical analysis and experimental investigation on a cryogenic reciprocating expander without moving piston. An intake valve which takes high-pressure gas, and an exhaust valve which discharges low-pressure gas, are connected to a tube. The inside pressure of the tube is pulsated for work production. This geometric configuration is similar to that of pulse tube refrigerator but without regenerator. An orifice valve and a reservoir are installed to control the phase of the mass flow and the pressure. At the warm end, a heat exchanger rejects the heat which is converted from the produced work of the expanded gas. For the numerical analysis, mass conservation, energy conservation, and local mass function for valves are used as the governing equations. Before performing cryogenic experiments, we carried out the expander test at room temperature and compared the performance results with the numerical results. For cryogenic experiments, the gas is pre-cooled by liquid nitrogen, and then it enters the pulse tube expander. The experiments are controlled by the opening of the orifice valve. Numerical analysis also found the expander conditions that optimize the expander performance by changing the intake pressure and valve timing as well as the opening of the orifice valve. This paper discusses the experimental data and the numerical analysis results to understand the fundamental behavior of such a newly developed non-mechanical expander and elucidate its potential feature for cryogenic application.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.26-35
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• 2005

Generally, we employ FSMs for the design of controllers in digital systems. FSMs are Implemented with state diagrams generated from control flow. With HDL, we design and verify FSMs based on state diagrams. As the number of states in the system increases, the verification or modification processes become complicated, error prone and time consuming. In this paper, we propose a control flow oriented hardware description language at the register transfer level called Cycle-C. Cycle-C describes FSMs with timing information and control How intensive algorithms. The Cycle-C description is automatically converted into FSMs in the form of synthesizable RTL VHDL. In experiments, we design FSMs for control intensive interface circuits. There is little area difference between Cycle-C design and manual design. In addition, Cycle-C design needs only 10~50% of the number lines of manual RTL VHDL designs.

• Journal of Service Research and Studies
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• v.1 no.1
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• pp.103-111
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• 2011

Smart phone products lead the mobile computing world really, and be expected as a major object of mobile phone market. In special, Android OS platform in smart phones is remarkedly uprising as of main software architecture. As many applications are applied as of the Location Based Service system in the perspective of technical support which represents open based technology. In this research, we developed the location information transformation service module, using LBS system, which effects some users urgently in the timing of traffic accidents. It supports to help some car drivers with smart phone, enables them to recognizes remote controller or another users.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.1
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• pp.109-119
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• 2013

This paper presents the design of the Safety Programmable Logic Controller (SPLC) used in the Nuclear Power Plants, an analysis of a reliability for the SPLC using a markov model. The architecture of the SPLC is designed to have the multiple modular redundancy composed of the Dual Modular Redundancy(DMR) and the Triple Modular Redundancy(TMR). The operating system of the SPLC is designed to have the non-preemptive state based scheduler and the supervisory task managing the sequential scheduling, timing of tasks, diagnostic and security. The data communication of the SPLC is designed to have the deterministic state based protocol, and is designed to satisfy the effective transmission capacity of 20Mbps. Using Markov model, the reliability of SPLC is analyzed, and assessed. To have the reasonable reliability such as the mean time to failure (MTTF) more than 10,000 hours, the failure rate of each SPLC module should be less than $2{\times}10^{-5}$/hour. When the fault coverage factor (FCF) is increased by 0.1, the MTTF is improved by about 4 months, thus to enhance the MTTF effectively, it is needed that the diagnostic ability of each SPLC module should be strengthened. Also as the result of comparison the SPLC and the existing safety grade PLCs, the reliability and MTTF of SPLC is up to 1.6-times and up to 22,000 hours better than the existing PLCs.

• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.6
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• pp.267-276
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• 2021

The automotive industry and academic research have been continuously conducting research on standardization such as AUTOSAR (AUTomotive Open System ARchitecture) and ISO26262 to solve problems such as safety and efficiency caused by the complexity of electric/electronic architecture of automotive. AUTOSAR is an automotive standard software platform that has a layered structure independent of MCU (Micro Controller Unit) hardware, and improves product reliability through software modularity and reusability. And, ISO26262, an international standard for automotive functional safety and suggests a method to minimize errors in automotive ECU (Electronic Control Unit)s by defining the development process and results for the entire life cycle of automotive electrical/electronic systems. These design methods are variously applied in representative automotive safety-critical systems. However, since the functional and safety requirements are different according to the characteristics of the safety-critical system, it is essential to research the AUTOSAR functional safety design method specialized for each application domain. In this paper, a software functional safety mechanism design method using AUTOSAR is proposed, and a new failure management framework is proposed to ensure the high reliability of the product. The AUTOSAR functional safety mechanism consists of memory partitioning protection, timing monitoring protection, and end-to-end protection. The fault management framework is composed of several safety SWCs to maintain the minimum function and performance even if a fault occurs during the operation of a safety-critical system. Finally, the proposed method is applied to the Shift-by-Wire system design to prove the validity of the proposed method.

• Journal of Biomedical Engineering Research
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• v.43 no.6
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• pp.375-381
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• 2022

Brain-computer interface (BCI) is a technology that allows users with motor disturbance to control machines by brainwaves without a physical controller. Motor imagery (MI)-BCI is one of the popular BCI techniques, but it needs a long calibration time for users to perform a mental task that causes high fatigue to the users. MI is reported as showing a similar neural mechanism as motor execution (ME) and motor observation (MO). However, integrative investigations of these three tasks are rarely conducted. In this study, we propose a new paradigm that incorporates three tasks (MI, ME, and MO) and conducted a comparative analysis. For this study, we collected Electroencephalograms (EEG) of motor imagery/execution/observation from 28 healthy subjects and investigated alpha event-related (de)synchronization (ERD/ERS) and classification accuracy (left vs. right motor tasks). As result, we observed ERD and ERS in MI, MO and ME although the timing is different across tasks. In addition, the MI showed strong ERD on the contralateral hemisphere, while the MO showed strong ERD on the ipsilateral side. In the classification analysis using a Riemannian geometry-based classifier, we obtained classification accuracies as MO (66.34%), MI (60.06%) and ME (58.57%). We conclude that there are similarities and differences in fundamental neural mechanisms across the three motor tasks and that these results could be used to advance the current MI-BCI further by incorporating data from ME and MO.

• Journal of Distribution Science
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• v.14 no.5
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• pp.51-57
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• 2016

Purpose - In the year of 2015 and 2016, one of the items that got attention in CES was a drone. It has been 100 years since a drone emerged, but most were used for military purposes. As its use became diverse as of 2010, it got attention of the general public. In Korea, it was in 2011 that a drone was known to the public through an aerial video shooting for television program. This study tried to come up with suggestions by comparing domestic with overseas cases, and tried to consider the related technologies and systems with applying the role of drones in logistics service. Research design, data, and methodology - The overseas cases were regarded as drone's logistical purpose. The Prime Air service by US Amazon is still not commercialized and under pre-testing due to Federal Aviation Regulations, although it started in 2013. In Germany, DHL succeeded in delivering service testing which is called Parcelcopter, but it is not commercialized yet. Other than these, there are more attempts to prepare logistics service in China with Taobao, in France with Geopost's test, and in Africa. In Korea, CJ Korea Express tested delivery with a self-developed drone Results - In order to study for utilizing drones for logistics as the prerequisites, some overseas and domestic cases, which are currently considered, were reviewed. Also, the technologies and institutional requirements to commercialize drones for logistical purpose were reviewed. The reasons for using drones in logistics is to ensure the price competitiveness by reducing cost. The empirical test also will be needed because drone pilot areas are designated by ministry of land, infrastructure and transport. Conclusions - In order to utilize drones in logistics and foster the industry, this study would like to suggest the followings. First of all, size of drones for logistics needs to be fixed and their operating system should be standardized. Centralized investment resources are needed through standardization to ensure the market occupancy. Secondly, it is necessary to get the converged businesses that do research, develop and commercialize drones with the investment of private sector. Example can be found in Korea aerospace Industries. We can respond to the rapid growth of the market with intensive investing by integrating the private sector investment. Thirdly, institutional arrangements are needed to be established quickly. In the case of high-technologies like drones, institutional support often does not follow the rapid development of the technology. The problems can be found in securing drones-only airspace, creating drone-specialized pilot's license, matters related to remote controller and complementary regulations for drones in Aviation Act. If these regulations are not prepared or complemented at the right timing, technologies cannot be commercialized even though the development is completed. Fourthly, there is a need to secure the transparency regarding possible privacy and personal information protection problem while operating drones. Finally, in order to foster this new industry, government should focus on supporting R&D more in the long term than short term outcomes.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.86-94
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• 2012

In this paper we propose a hardware architecture of high-speed CGH (computer generated hologram) generation processor, which particularly reduces the number of memory access times to avoid the bottle-neck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation rather than light source-by-source calculation. The second is parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last one is a fully pipelined calculation scheme and exactly structured timing scheduling by adjusting the hardware. The proposed hardware is structured to calculate a row of a CGH in parallel and each hologram pixel in a row is calculated independently. It consists of input interface, initial parameter calculator, hologram pixel calculators, line buffer, and memory controller. The implemented hardware to calculate a row of a $1,920{\times}1,080$ CGH in parallel uses 168,960 LUTs, 153,944 registers, and 19,212 DSP blocks in an Altera FPGA environment. It can stably operate at 198MHz. Because of the three schemes, the time to access the external memory is reduced to about 1/20,000 of the previous ones at the same calculation speed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.683-694
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• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.