• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.365-375
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• 2014

This paper proposes an abnormal V-shaped-error-free non-blind deconvolution technique featuring an adaptively segmented forward-problem based iterative deconvolution (ASDCN) process. Unlike the algebraic based inverse operations, this eliminates any operations of differential and division by zero to successfully circumvent the issue on the abnormal V-shaped error. This effectiveness has been demonstrated for the first time with applying to a real analysis for the effects of the Random Telegraph Noise (RTN) and/or Random Dopant Fluctuation (RDF) on the overall SRAM margin variations. It has been shown that the proposed ASDCN technique can reduce its relative errors of RTN deconvolution by $10^{13}$ to $10^{15}$ fold, which are good enough for avoiding the abnormal ringing errors in the RTN deconvolution process. This enables to suppress the cdf error of the convolution of the RTN with the RDF (i.e., fail-bit-count error) to $1/10^{10}$ error for the conventional algorithm.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.164-170
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• 2004

Misfiring is often observed during the high temperature quality assurance test of plasma display panel. This limits the productivity of PDP industry. In this paper, experimental observations on the misfiring at high panel temperature have been performed through time dependent discharge light output and static margin measurement. For the high temperature condition, firing voltage increment is found in both surface and facing discharges. This in turn increases time lag in address discharge, and results in increment of misfiring probability. In order to reduce this kind of misfiring, a new method that applies automatically different slope of ramp erasing pulse on the common electrode according to temperature variation is proposed. The experimental results show that controlling the slope of ramp erasing pulse is quite effective for compensating temperature-dependent variation of reset and address discharge.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.1755-1758
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• 2004

Misfiring is often observed during the high temperature quality assurancetest of plasma display panel. This limits the productivity of PDP industry. In this paper, experimental observations on the misfiring at high panel temperature have been performed through time dependent discharge light output and static margin measurement. For the high temperature condition, firing voltage increment is found in both surface and facing discharges. This in turn increases lime lag in address discharge, and results m increment of misfiring probability. In order to reduce this kind of misfiring, a new method that applies automatically different slope of ramp erasing pulse on the common electrode according to temperature variation is proposed. The experimental results show that controlling the slope of ramp erasing pulse is quite effective for compensating temperature-dependent variation of reset and address discharge.