• Convergence Security Journal
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• v.7 no.2
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• pp.17-25
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• 2007

In this paper, an algorithm that provisions proportional differentiation of packet delays is proposed with an objective for enhancing quality of service (QoS) in future packet networks. It features an adaptive scheme that adjusts the target delay every time slot to compensate the deviation from the target delay which is caused by the prediction error on the traffic to be arrived in the next time slot. It predicts the traffic to be arrived at the beginning of a time slot and measures the actual arrived traffic at the end of the time slot. The difference between them is utilized to the delay control operation for the next time slot to offset it. As it compensates the prediction error continuously, it shows superior adaptability to the bursty traffic as well as the exponential rate traffic. It is demonstrated through simulations that the algorithm meets the quantitative delay bounds and shows superiority to the traffic fluctuation in comparison with the conventional non-adaptive mechanism. The algorithm is implemented with VHDL on a Xilinx Spartan XC3S1500 FPGA and the performance is verified under the test board based on the XPC860P CPU.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.3
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• pp.417-422
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• 2021

In this paper, a ZQ calibration using a time domain comparator is proposed. The proposed comparator is designed based on VCO, and an additional clock generator is used to reduce power consumption. By using the proposed comparator, the reference voltage and the PAD voltage were compared with a low 1 LSB voltage, so that the additional offset cancelation process could be omitted. The proposed time domain comparator-based ZQ calibration circuit was designed with a 65nm CMOS process with 1.05V and 0.5V supply voltages. The proposed clock generator reduces power consumption by 37% compared to a single time domain comparator, and the proposed ZQ calibration increases the mask margin by up to 67.4%.

• Journal of Positioning, Navigation, and Timing
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• v.11 no.4
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• pp.287-295
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• 2022

The GNSS coordinate time series is used as important data for geophysical analysis such as terrestrial reference frame establishment, crustal deformation, Earth orientation parameter estimation, etc. However, various factors may cause discontinuity in the coordinate time series, which may lead to errors in the interpretation. In this paper, we describe the discontinuity in the coordinate time series due to the equipment replacement for domestic GNSS stations and discuss the change in movement magnitude and velocity vector difference in each direction before and after discontinuity correction. To do this, we used three years (2017-2019) of data from 40 GNSS stations. The average magnitude of the velocity vector in the north-south, east-west, and vertical directions before correction is -12.9±1.5, 28.0±1.9, and 4.2±7.6 mm/yr, respectively. After correction, the average moving speed in each direction was -13.0±1.0, 28.2±0.8, and 0.7±2.1 mm/yr, respectively. The average magnitudes of the horizontal GNSS velocity vectors before and after discontinuous correction was similar, but the deviation in movement size of stations decreased after correction. After equipment replacement, the change in the vertical movement occurred more than the horizontal movement variation. Moreover, the change in the magnitude of movement in each direction may also cause a change in the velocity vector, which may lead to errors in geophysical analysis.

• Journal of Auto-vehicle Safety Association
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• v.13 no.2
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• pp.35-41
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• 2021

In this study, improved path tracking control algorithm based on pure pursuit algorithm is newly proposed by using improved lane detection algorithm through real time post-processing with interpolation methodology. Since the original pure pursuit works well only at speeds below 20 km/h, the look-ahead distance is implemented as a sigmoid function to work well at an average speed of 45 km/h to improve tracking performance. In addition, a smoothing filter was added to reduce the steering angle vibration of the original algorithm, and the stability of the steering angle was improved. The post-processing algorithm presented has implemented more robust lane recognition system using real-time pre/post processing method with deep learning and estimated interpolation. Real time processing is more cost-effective than the method using lots of computing resources and building abundant datasets for improving the performance of deep learning networks. Therefore, this paper also presents improved lane detection performance by using the final results with naive computer vision codes and pre/post processing. Firstly, the pre-processing was newly designed for real-time processing and robust recognition performance of augmentation. Secondly, the post-processing was designed to detect lanes by receiving the segmentation results based on the estimated interpolation in consideration of the properties of the continuous lanes. Consequently, experimental results by utilizing driving guidance line information from processing parts show that the improved lane detection algorithm is effective to minimize the lateral offset error in the diverse maneuvering roads.

• Journal of IKEEE
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• v.26 no.1
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• pp.10-18
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• 2022

Accurate SOC estimation is an important indicator of battery operation strategies, and many studies have been conducted. The simulation method which was mainly used in previous studies, is difficult to conduct real-time SOC estimation like real BMS environment. Therefore, this paper aims to implement a real-time battery SOC estimation embedded system and analyze problems that can arise during the verification process. In environment consisting of two Raspberry Pi boards, SOC estimation with the EKF uses data measured by the Simscape battery model. Considering that the operating characteristics of the battery vary depend on the temperature, the results were analyzed at various ambient temperatures. It was confirmed that accurate SOC estimation was performed even when offset fault and packet loss occurred due to communication or sensing problems. This paper proposes a guide for embedded system strategies that enable real-time SOC estimation with errors within 5%.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.7 s.337
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• pp.35-40
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• 2005

This paper proposes a fractional-N phase-locked loop (PLL) frequency synthesizer using the 3rd order ${\Delta}{\sum}$ modulator for 900MHz medium speed wireless link. The LC voltage-controlled oscillator (VCO) is used for the good phase noise property. To reduce the lock-in time, a charge pump has been developed to control the pumping current according to the frequency steps and the reference frequency is increased up to 3MHz. A 36/37 fractional-N divider is used to increase the reference frequency of the phase frequency detector (PFD) and to reduce the minimum frequency step simultaneously. A 3rd order ${\Delta}{\sum}$ modulator has been developed to reduce the fractional spur VCO, Divider by 8 Prescaler, PFD and Charge pump have been developed with 0.25um CMOS, and the fractional-N divider and the third order ${\Delta}{\sum}$ modulator have been designed with the VHDL code, and they are implemented through the FPGA board of the Xilinx Spartan2E. The measured results show that the output power of the PLL is about -lldBm and the phase noise is -77.75dBc/Hz at 100kHz offset frequency. The minimum frequency step and the maximum lock-in time are 10kHz and around 800us for the maximum frequency change of 10MHz, respectively.

• Journal of Astronomy and Space Sciences
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• v.21 no.4
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• pp.399-416
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• 2004

The FIMS (Far-ultraviolet IMaging Spectrograph), the main payload onboard the first Korean science satellite STSAT-1, has performed various observations since its launch on September 2003. It has been found that the attitude informations provided by spacecraft bus system have a time offset problem, and the problem has been extensively studied. After the time offset correction, boresight offsets between FIMS fields of view, of long and short wavelength bands, respectivley, and spacecraft attitude systems, which are mainly due to alignment error between the FIMS and spacecraft mechanical systems, were calculated through the observations of well known calibration targets. Monthly status and precision of the attitude information are also described. Correction methods for spatially variable exposure, intrinsic to FIMS data, are discussed. These results are essential to the FIMS data analysis, and will be used as references for subsequent studies on more accurate attitude corrections.

• Journal of Advanced Navigation Technology
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• v.18 no.3
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• pp.215-222
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• 2014

In this paper, parafoil airdrop system has been designed and analyzed. 6-degrees of freedom (6-DOF) model of the parafoil system is set up. Nonlinear model predictive control (NMPC) and Proportion integration differentiation (PID) methods were separately applied to adjust the flap yaw angle. Compared the results of setting time and overshoot time of yaw angle, it is found that the of yaw angle is more stable by using PID method. Then, trajectory following controller was designed based on the simulation results of trajectory following effects, which was carried out by using MATLAB. The lateral offset error of parafoil trajectory can be eliminated by its lateral deviation control. The later offset deviation reference was obtained by the interpolation of the current planning path. Moreover, using the designed trajectory, the trajectory following system was simulated by adding the wind disturbances. It is found that the simulation result is highly agreed with the designed trajectory, which means that wind disturbances have been eliminated with the change of yaw angle controlled by PID method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.3C
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• pp.302-313
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• 2010

In this paper, we propose an enhanced AGC (Automatic Gain Control) structure and P-SCH detection method for initial cell search in 3GPP (3rdGenerationPartnershipProject) LTE (Long Term Evolution) FDD(Frequency Division Duplex) / TDD (Time Division Duplex) dual mode system. Since TDD frame structure consists of uplink subframe and downlink subframe, conventional AGC structure causes P-SCH detection performance degradation by increase of AGC variation due to signal power difference between uplink and downlink subframe. Also, P-SCH detection performance is degraded by distortion of P-SCH correlation characteristic in frequency offset and multipath fading channel environments. Therefore, we propose an AGC structure which can minimize P-SCH detection performance degradation with stable operation in 3GPP LTE TDD mode as well as FDD mode. Also we propose a P-SCH detection method which can reduce distortion of correlation chareteristics in frequency offset and multipath fading environments and obtain good P-SCH detection performance. Simulation results show that the proposed AGC structure and P-SCH detection method have stable AGC operation and excellent P-SCH detection performance for 3GPP LTE TDD / FDD dual mode downlink receiver in various channel environments.