• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.937-940
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• 2007

오늘날 대부분의 임베디드 시스템에서 사용하는 uClinux에서 기본적으로 프로세스가 이용할 수 있는 범위의 시스템 클럭은 10m/s 이상이다. 기존에는 무리하게 시스템 클럭의 속도를 무리하게 높여 더 높은 정밀도를 요구하는 프로세스를 처리해 왔다. 이는 시스템 리소스를 많이 사용함과 동시에 타이머 인터럽트를 처리하는 오버헤드도 상대적으로 증가하여 전체적으로 시스템의 성능과 안정성에 좋지 못했다. 이에 본 논문에서는 uClinux기반의 임베디드 장치와 Real-Time Clock(RTC)모듈과의 인터페이스 최적화 방안에 관하여 제안한다. 이로써 시스템 클럭을 사용하지 않고, RTC 자체의 인터럽트를 사용해서 작업을 진행해 나가기 때문에 시스템 리소스를 적게 사용하며, 시스템의 성능에 영향을 적게 준다. 또한 알고리즘적인 최적화를 사용 코드최적화를 사용하여 임베디드 시스템에서 가장 효율적으로 관리해야할 리소스인 메모리를 절약, 기존의 방식과 차별을 두었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.2
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• pp.417-426
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• 1996

The end-to-end service clock recovery is a critical issue in providing constandt bit rate service through ATM network. The Synchronous Residual Time Stamp(SRTS) algorithm is used to recovery the source clock using time stamp of transmitter. In thispaper, we propose a Differential Residual Time Stamp (DRTS) transmission mechanism to effectively deliver the timing information of source clock in SRTS algorithm. The RTS transmission method simple in its hardware. From the results of field trial of DS3 rate interactive video communication system through B-ISDN testbed, it can be identified that DRTS method is superior to the RTS method.

• Journal of Electrical Engineering and Technology
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• v.13 no.6
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• pp.2479-2484
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• 2018

The filter bank multicarrier modulation (FBMC) technique is one of multicarrier modulation technique (MCM), which is mainly used to improve channel capacity of cognitive radio (CR) network and frequency spectrum access technique. The existing FBMC System contains serial to parallel converter, normal QAM modulation, Radix2 inverse FFT, parallel to serial converter and poly phase filter. It needs high area, delay and power consumption. To further reduce the area, delay and power of FBMC structure, a new clock gating technique is applied in the QAM modulation, radix2 multipath delay commutator (R2MDC) based inverse FFT and unified addition and subtraction (UAS) based FIR filter with parallel asynchronous self time adder (PASTA). The clock gating technique is mainly used to reduce the unwanted clock switching activity. The clock gating is nothing but clock signal of flip-flops is controlled by gate (i.e.) AND gate. Hence speed is high and power consumption is low. The comparison between existing QAM and proposed QAM with clock gating technique is carried out to analyze the results. Conversely, the proposed inverse R2MDC FFT with clock gating technique is compared with the existing radix2 inverse FFT. Also the comparison between existing poly phase filter and proposed UAS based FIR filter with PASTA adder is carried out to analyze the performance, area and power consumption individually. The proposed FBMC with clock gating technique offers low power and high speed than the existing FBMC structures.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.415-417
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• 2005

Core operations (e.9. TDMA scheduler, synchronized sleep period, data aggregation) of many proposed protocols for different layer of sensor network necessitate clock synchronization. Our Paper mingles the scheme of dynamic clustering and diffusion based asynchronous averaging algorithm for clock synchronization in sensor network. Our proposed algorithm takes the advantage of dynamic clustering and then applies asynchronous averaging algorithm for synchronization to reduce number of rounds and operations required for converging time which in turn save energy significantly than energy required in diffusion based asynchronous averaging algorithm.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.3
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• pp.67-78
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• 2013

In this paper, We proposed an development method of application framework for using the precision time protocol(PTP) based on physical layer devices to synchronize clocks across a network with IEEE1588 capable devices. The algorithm was not designed as a complete solution across all conditions, but is intended to show the feasibility of such a for the PTP(Precision Time Protocol) based on time synchronization of heterogeneous network between devices that support in IEEE 1588 Standard application framework. With synchronization messages per second, the system was able to accurately synchronize across a single heavily loaded switch. we describes a method of synchronization that provides much more accurate synchronization in systems with larger networks. In this paper, using the IEEE 1588 PTP support for object-oriented modeling techniques through the 'application framework development Development(AFDM)' is proposed. The method described attempts to detect minimum delays, or precision packet probe and packet metrics. The method also takes advantage of the Tablet PC(Primary to Secondary) clock control mechanism to separately control clock rate and time corrections, minimizing overshoot or wild swings in the accuracy of the clock. We verifying the performance of PTP Systems through experiments that proposed method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2218-2226
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• 2009

TDMA based MAC protocol supporting wireless mesh network has many advantage rather than 802.11 DCF/EDCA protocol based on packet. But TDMA based MAC protocol require new synchronization method because of mobile point oscillator's difference, and distributed environments. This thesis propose synchronization method for TDMA based MAC protocol. It divides MP(Mobile Points) states into 4 types. If MP is in sync mode, it schedules TDMA local start time in time skew interval using beacon. It proposes compensation algorithms to compensate time skew caused by clock drift. This proposal show that general time error and clock drift rate value reduced and get synchronized result.

• Proceedings of the KSRS Conference
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• 2008.10a
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• pp.277-280
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• 2008

Enhancing the positioning precision is the primary pursuit of GPS users. To achieve this goal, most studies have focused on the relationship between GPS receiver clock errors and GPS positioning precision. This study utilizes undifferentiated phase data to calculate GPS clock errors and to compare with the frequency of cesium clock directly, thus verifying estimated clock errors by the method used in this paper. The relative frequency offsets from this paper and from National Standard Time and Frequency Laboratory of Taiwan match to $1.5{\times}10^{12}$ in the frequency instability, suggesting that the proposed technique has reached a certain level of quality. The built-in quartz clocks in the GPS receivers yield relative frequency offsets that are 3 to 4 orders higher than those of rubidium clocks. The frequency instability of the quartz clocks is on average two orders worse than that of the rubidium clock. Using the rubidium clock instead of the quartz clock, the horizontal and vertical positioning accuracies were improved by 26-78% (0.6-3.6 mm) and 20-34% (1.3-3.0 mm), respectively, for a short baseline. These improvements are 7-25% (0.3-1.7 mm) and 11% (1.7 mm) for a long baseline. Our experiments show that the frequency instability of clock, rather than relative frequency offset, is the governing factor of positioning accuracy.

• Journal of Korea Multimedia Society
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• v.10 no.3
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• pp.348-357
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• 2007

One of the major issues in recent researches on wireless sensor networks is to reduce energy consumption of sensor nodes operating with limited battery power, in order to lengthen their lifespan. Among the researches, we are interested in the schemes in which a sensor node periodically turns on and off its radio and requires information on the time when its neighbors will wake up (or turn on). Clock synchronization is essential for wakeup scheduling in such schemes. This paper proposes three methods based on the asynchronous averaging algorithm for clock synchronization in sensor nodes which periodically wake up: (1) a fast clock synchronization method during an initial network construction period, (2) a periodic clock synchronization method for saving energy consumption, and (3) a decision method for switching the operation mode of sensor nodes between the two clock synchronization methods. Through simulation, we analyze maximum clock difference and the number of messages required for clock synchronization.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.1
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• pp.395-400
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• 2006

Among the various error sources in positioning and navigation, the paper focuses on the modeling and prediction of receiver clock bias and then tries to achieve positioning based on simulated and predicted clock bias. With the SA off, it is possible to model receiver clock bias more accurately. We selected several types of GNSS receivers for test using ARMA model. To facilitate prediction with short and limited sample pseudorange observations, AR and ARMA are compared, and the improved AR model is presented to model and predict receiver clock bias based on previous solutions. Our work extends to clock bias prediction and positioning based on predicted clock bias using only 3 satellites that is usually the case under urban canyon situation. In contrast to previous experiences, we find that a receiver clock bias can be well modeled using adopted ARMA model. Test has been done on various types of GNSS receivers to show the validation of developed model. To further develop this work, we compare solution conditions in terms of DOP values when point positioning is conducted using 3 satellites to simulate urban positioning environment. When condition allows, height component is derived from other ways and can be set as known values. Given this condition, location is possible using less than 2 GNSS satellites with fixed height. Solution condition is also discussed for this background using mode of constrained positioning. We finally suggest an effective predictive time span based on our test exploration under varied conditions.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.4
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• pp.331-339
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• 2018

The IEEE 1588, commonly known as a precision time protocol (PTP), is a standard for precise clock synchronization that maintains networked measurements and control systems. The best master clock (BMC) algorithm is currently used to establish the master-slave hierarchy for PTP. The BMC allows a slave clock to automatically take over the duties of the master when the slave is disconnected due to a link failure and loses its synchronization; the slave clock depends on a timer to compensate for the failure of the master. However, the BMC algorithm does not provide a fast recovery mechanism in the case of a master failure. In this paper, we propose a technique that combines the IEEE 1588 with network bonding to provide a faster recovery mechanism in the case of a master failure. This technique is implemented by utilizing a pre-existing library PTP daemon (Ptpd) in Linux system, with a specific profile of the IEEE 1588 and it's controlled through bonding modes. Network bonding is a process of combining or joining two or more network interfaces together into a single interface. Network bonding offers performance improvements and redundancy. If one link fails, the other link will work immediately. It can be used in situations where fault tolerance, redundancy, or load balancing networks are needed. The results show combining IEEE 1588 with network bonding enables an incredible shorter recovery time than simply just relying on the IEEE 1588 recovery method alone.