• Journal of IKEEE
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• v.19 no.4
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• pp.590-595
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• 2015

This paper proposes a design of efficient hierarchy structure in the tile based rasterizer. The proposed hierarchy structure avoids unnecessary calls of low level tile at which a calculation is not required. A low level tile is classified into three categories based on its maximum, minimum position, and inside outside test. The necessity of calculations on the corresponding low level tile can be determined by its classification. The overall amount of computations for graphic processing can be reduced by not calling for the low level tile with no calculation. The proposed hierarchy structure can reduce an execution time of graphic processing. It shows higher efficiency with the more vertex density of formulating 3D model.

• Journal of IKEEE
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• v.18 no.3
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• pp.403-408
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• 2014

In this paper, we propose a rasterizer architecture using varying interpolator which process several pixels at a time. Proposed rasterizer is able to handle 16 pixel at a time and output the color of up to 64. It can reduce the redundancy of calculation by configuring a matrix transformation and matrix calculation for rasterization, and it can enhance the speed of rasterizer by increasing the reusability. As a result, proposed rasterizer has improve 11% in color interpolation, 17% in the processing speed of the rasterizer by comparing with conventional research.