• Journal of IKEEE
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• v.20 no.1
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• pp.75-81
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• 2016

This paper proposes a design of the tile based on graphic pipeline to improve the graphic application performance in SIMT based GP-GPU. The proposed Tile based on graphics pipeline avoids unnecessary graphic processing operation, and processes the rasterization step in parallel. The massive data processing in parallel through SIMT architecture improve the computational performance, thereby improving the 3D graphic pipeline performance. The more vertex data of 3D model, the higher performance. The proposed structure was confirmed to improve processing performance of up to 3 times from about 1.18 times as compared to 'RAMP' and previous studies.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.309-311
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• 2014

The tile-based rendering technique which divides the screen area into tiles of a specific size and creates a 3D graphic model of one tile at a time is used to efficiently utilize limited resources in a 3D graphic pipeline. In this paper, the tiling speed of tile-based rendering was improved by reducing the count of calling lower-levels in the hierarchical tile-based rendering technique. The tiling speed of the proposed Rasterizer is 13.030ms which is 56% faster than 29.614ms of multi-sort tiling and 24% faster than 17.208ms of the conventional hierarchical tiling technique.