• Title/Summary/Keyword: thin film

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a-Si:H TFT Using Ferroelectrics as a Gate Insulator (강유전체를 게이트 절연층으로 한 수소화 된 비정질실리콘 박막 트랜지스터)

  • 허창우;윤호군;류광렬
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2003.10a
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    • pp.537-541
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    • 2003
  • The a-Si:H TFTs using ferroelectric of SrTiO$_3$, as a gate insulator is fabricated on glass. Dielectric characteristics of ferroelectric is better than SiO$_2$, SiN. Ferroelectric increases ON-current, decreases threshold voltage of TFT and also breakdown characteristics. The a-Si:H deposited by PECVD shows absorption band peaks at wavenumber 2,000 $cm^{-1}$ /, 635 $cm^{-1}$ / and 876 $cm^{-1}$ / according to FTIR measurement. Wavenumber 2,000 $cm^{-1}$ /, 635 $cm^{-1}$ / are caused by stretching and rocking mode SiH1. The wavenumber of weaker band, 876 $cm^{-1}$ / is due to SiH$_2$ vibration mode. The a-SiN:H has optical bandgap of 2.61 eV, refractive index of 1.8 - 2.0 and resistivity of 10$^{11}$ - 10$^{15}$ aim respectively. Insulating characteristics of ferroelectric is excellent because dielectric constant of ferroelectric is about 60 - 100 and breakdown strength is over 1 MV/cm. TFT using ferroelectric has channel length of 8 - 20 $\mu$m and channel width of 80 - 200 $\mu$m. And it shows drain current of 3 $\mu$A at 20 gate voltages, Ion/Ioff ratio of 10$^{5}$ - 10$^{6}$ and Vth of 4 - 5 volts.

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A Study on the Measurements of Sub-surface Residual Stress in the Field of Linear Stress Gradient (선형구배 응력장에서 표층의 잔류응력 측정에 관한 연구)

  • 최병길;전상윤;이택순
    • Transactions of the Korean Society of Mechanical Engineers
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    • v.16 no.9
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    • pp.1632-1642
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    • 1992
  • When a blind hole of small diameter is drilled in the field of residual stress, strain relieved around the hole is function of magnitude of stress, patterns of stress distribution and hole geometry of diameter and depth. Relieved strain coefficients can be calculated from FEM analysis of relieved strain and actual stress. These relieved strain coefficients make it possible to measure residual stress which vary along the depth in the subsurface of stressed material. In this study, the calibration tests of residual stress measurement are carried out by drilling a hole incrementally on the cantilever or on the tensile test bar. Residual stresses can be determined from measured strains around a shallow hole by application of power series method. For the sake of reliable measurement of residual stress, much efforts should be done to measure relieved strains and hole depth more accurately comparing with conventional procedures of gage subject to the external load. Otherwise linear equations converting strains into stresses may yield erratic residual stresses because of ill-conditions of linear equations. With accurate measurements of relieved strains, residual stress even if varying along the depth can be measured. It is also possible to measure residual stress in the thin film of material by drilling a shallow hole.

The Effects of Metal Plate loaded on TLD chip in 6 MV Photon and 6 MeV Electron Beams (6 MV 광자선과 6 MeV 전자선 하에서 TLD 기판 위에 얹힌 금속 박막의 효과)

  • Kim, Sookil;Byungnim Min
    • Progress in Medical Physics
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    • v.10 no.1
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    • pp.41-46
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    • 1999
  • There is necessity for making a smaller and more sensitive detector in small field sizes. This report assesses the suitability of metal-loaded thermoluminescent dosimeters for this purpose. Measurements were performed in the 6 MV photon and 6 MeV electron beams of a medical linear accelerator with LiF thermoluminescence dosimeters (TLD-100) embedded in solid water phantom. TLD-100 chips(surface area 3.2 $\times$ 3.2 $\textrm{mm}^2$) loaded with a metal plate(Tin or gold respectively) were used to enhance dose readings to TLD-100. Surface dose was measured for field size 10 $\times$ 10 $\textrm{cm}^2$ and 100 em SSD. Measurements have been made of the enhanced signal intensity and good linearity for absorbed dose with each metal. Using a 1 mm each metal on TLD-l00 in the beam increased the surface dose to 14% and 56% respectively for 6MV photon. In the case of 6 MeV electron, gold plate enhanced the TL response to 13%, but there is no difference for tin plate. The specific dose response of TLD-100 with thin metal plate increases with electron concentration of metal film, this is most likely due to increased electron scattered from the additional material with electron density higher than TLD-100. This emphasizes the role of TL dosimeters with metal as amplified dosimeters for therapeutic high energy x-ray beams. Due to the enhanced dose reading of TLD-100 with metal plate, it could be possible to develop smaller TL dosimeter with high sensitivity.

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PECVD를 이용한 2차원 이황화몰리브데넘 박막의 저온합성법 개발

  • Kim, Hyeong-U;An, Chi-Seong;Arabale, Girish;Lee, Chang-Gu;Kim, Tae-Seong
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.274-274
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    • 2014
  • 금속칼코게나이드 화합물중 하나인 $MoS_2$는 초저 마찰계수의 금속성 윤활제로 널리 사용되고 있으며 흑연과 비슷한 판상 구조를 지니고 있어 기계적 박리법을 통한 그래핀의 발견 이후 2차원 박막 합성법에 대한 활발한 연구가 진행되고 있다. 최근 다양한 응용이 진행 중인 그래핀의 경우 높은 전자이동도, 기계적 강도, 유연성, 열전도도 등 뛰어난 물리적 특성을 지니고 있으나 zero-bandgap으로 인한 낮은 on/off ratio는 thin film transistor (TFT), 논리회로(logic circuit) 등 반도체 소자 응용에 한계가 있다. 하지만 $MoS_2$는 벌크상태에서 약 1.2 eV의 indirect band-gap을 지닌 반면 단일층의 경우 1.8 eV의 direct-bandgap을 나타내고 있다. 또한 단일층 $MoS_2$를 이용하여 $HfO_2/MoS_2/SiO_2$ 구조의 트랜지스터를 제작하였을 때 $200cm^2/v^{-1}s^{-1}$의 높은 mobility와 $10^8$ 이상의 on/off ratio 나타낸다는 연구가 보고되어 있어 박막형 트랜지스터 응용을 위한 신소재로 주목을 받고 있다. 한편 2차원 $MoS_2$ 박막을 합성하기 위한 대표적인 방법인 기계적 박리법의 경우 고품질의 단일층 $MoS_2$ 성장이 가능하지만 대면적 합성에 한계를 지니고 있으며 화학기상증착법(CVD)의 경우 공정 gas의 분해를 위한 높은 온도가 요구되므로 박막형 투명 트랜지스터 응용을 위한 플라스틱 기판으로의 in-situ 성장이 어렵기 때문에 이를 보완할 수 있는 $MoS_2$ 박막 합성 공정 개발이 필요하다. 특히 Plasma enhanced chemical vapor deposition (PECVD) 방법은 공정 gas가 전기적 에너지로 분해되어 chamber 내부에서 cold-plasma 형태로 존 재하기 때문에 박막의 저온성장 및 대면적 합성이 가능하며 고진공을 바탕으로 합성 중 발생하는 오염 요소를 효과적으로 제어할 수 있다. 본 연구에서는PECVD를 이용하여 plasma power, 공정압력, 공정 gas의 유량 등 다양한 공정 변수를 조절함으로써 저온, 저압 조건하에서의 $MoS_2$ 박막 성장 가능성을 확인하였으며 전구체로는 Mo 금속과 $H_2S$ gas를 사용하였다. 또한 향후 flexible 소자 응용을 위한 플라스틱 기판의 녹는점을 고려하여 공정 온도는 $300^{\circ}C$ 이하로 설정하였으며 합성된 $MoS_2$ 박막의 두께 및 화학적 구성은 Raman spectroscopy를 이용하여 확인 하였다. 공정온도 $200^{\circ}C$$150^{\circ}C$에서 성장한 $MoS_2$ 박막의 Raman peak의 경우 상대적으로 낮은 공정온도로 인하여 Mo와 H2S의 화학적 결합이 감소된 것을 관찰할 수 있었고 $300^{\circ}C$의 경우 약 $26{\sim}27cm^{-1}$의 Raman peak 간격을 통해 5~6층의 $MoS_2$ 박막이 형성 된 것을 확인할 수 있었다.

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Development of an Improved Numerical Methodology for Design and Modification of Large Area Plasma Processing Chamber

  • Kim, Ho-Jun;Lee, Seung-Mu;Won, Je-Hyeong
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.221-221
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    • 2014
  • The present work proposes an improved numerical simulator for design and modification of large area capacitively coupled plasma (CCP) processing chamber. CCP, as notoriously well-known, demands the tremendously huge computational cost for carrying out transient analyses in realistic multi-dimensional models, because electron dissociations take place in a much smaller time scale (${\Delta}t{\approx}10-8{\sim}10-10$) than time scale of those happened between neutrals (${\Delta}t{\approx}10-1{\sim}10-3$), due to the rf drive frequencies of external electric field. And also, for spatial discretization of electron flux (Je), exponential scheme such as Scharfetter-Gummel method needs to be used in order to alleviate the numerical stiffness and resolve exponential change of spatial distribution of electron temperature (Te) and electron number density (Ne) in the vicinity of electrodes. Due to such computational intractability, it is prohibited to simulate CCP deposition in a three-dimension within acceptable calculation runtimes (<24 h). Under the situation where process conditions require thickness non-uniformity below 5%, however, detailed flow features of reactive gases induced from three-dimensional geometric effects such as gas distribution through the perforated plates (showerhead) should be considered. Without considering plasma chemistry, we therefore simulated flow, temperature and species fields in three-dimensional geometry first, and then, based on that data, boundary conditions of two-dimensional plasma discharge model are set. In the particular case of SiH4-NH3-N2-He CCP discharge to produce deposition of SiNxHy thin film, a cylindrical showerhead electrode reactor was studied by numerical modeling of mass, momentum and energy transports for charged particles in an axi-symmetric geometry. By solving transport equations of electron and radicals simultaneously, we observed that the way how source gases are consumed in the non-isothermal flow field and such consequences on active species production were outlined as playing the leading parts in the processes. As an example of application of the model for the prediction of the deposited thickness uniformity in a 300 mm wafer plasma processing chamber, the results were compared with the experimentally measured deposition profiles along the radius of the wafer varying inter-electrode gap. The simulation results were in good agreement with experimental data.

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Contact Transfer Printing Using Bi-layer Functionalized Nanobio Interface for Flexible Plasmonic Sensing

  • Lee, Jihye;Park, Jiyun;Lee, Junyoung;Yeo, Jong-Souk
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.413-413
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    • 2014
  • In this paper, we present a fabrication method of functionalized gold nanostructures on flexible substrate that can be implemented for plasmonic sensing application. For biomolecular sensing, many researchers exploit unconventional lithography method like nanoimprint lithography (NIP), contact transfer lithography, soft lithography, colloidal transfer printing due to its usability and easy to functionalization. In particular, nanoimprint and contact transfer lithography need to have anti-adhesion layer for distinctive metallic properties on the flexible substrates. However, when metallic thin film was deposited on the anti-adhesion layer coated substrates, we discover much aggravation of the mold by repetitive use. Thus it would be impossible to get a high quality of metal nanostructure on the transferred substrate for developing flexible electronics based transfer printing. Here we demonstrate a method for nano-pillar mold and transfer the controllable nanoparticle array on the flexible substrates without an anti-adhesion layer. Also functionalization of gold was investigated by the different length of thiol applied for effectively localized surface plasmonic resonance sensing. First, a focused ion beam (FIB) and ICP-RIE are used to fabricate the nanoscale pillar array. Then gold metal layer is deposited onto the patterned nanostructure. The metallic 130 nm and 250 nm nanodisk pattern are transferred onto flexible polymer substrate by bi-layer functionalized contact imprinting which can be tunable surface energy interfaces. Different thiol reagents such as Thioglycolic acid (98%), 3-Mercaptopropionic acid (99%), 11-Mercaptoundecanoic acid (95%) and 16-Mercaptohexadecanoic acid (90%) are used. Overcoming the repeatedly usage of the anti-adhesion layer mold which has less uniformity and not washable interface, contact printing method using bi-layer gold array are not only expedient access to fabrication but also have distinctive properties including anti-adhesion layer free, functionalized bottom of the gold nano disk, repeatedly replicate the pattern on the flexible substrate. As a result we demonstrate the feasibility of flexible plasmonic sensing interface and anticipate that the method can be extended to variable application including the portable bio sensor via mass production of stable nanostructure array and other nanophotonic application.

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A Study on the Removal of Cu and Fe Impurities on Si Substrate (Si 기판에서 구리와 철 금속불순물의 제거에 대한 연구)

  • Choi, Baik-Il;Jeon, Hyeong-Tag
    • Korean Journal of Materials Research
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    • v.8 no.9
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    • pp.837-842
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    • 1998
  • As the size of the integrated circuit is scaled down the importance of Si cleaning has been emphasized. One of the major concerns is abut the removal of metallic impurities such as Cu and Fe on Si surface. In this study, we intentionally contaminated Cu and Fe on the Si wafers and cleaned the wafer by cleaning splits of the chemical mixture of $\textrm{H}_2\textrm{O}_2$ and HF and the combination of HF treatment with UV/$\textrm{O}_3$ treatment. The contamination level was monitored by TXRF. Surface microroughness of the Si wafers was measured by AFM. The Si wafer surface was examined by SEM. AES analysis was carried out to analyze the chemical composition of Cu impurities. The amount of Cu impurities after intentional contamination was abut the level of $\textrm{10}^{14}$ atoms/$\textrm{cm}^2$. The amount of Cu was decreased down to the level of $\textrm{10}^{10}$ atoms/$\textrm{cm}^2$ by cleaning splits. The repeated treatment exhibited better Cu removal efficiency. The surface roughness caused by contamination and removal of Cu was improved by repeated treatment of the cleaning splits. Cu were adsorbed on Si surface not in a thin film type but in a particle type and its diameter was abut 100-400${\AA}$ and its height was 30-100${\AA}$. Cu was contaminated on Si surface by chemical adsorption. In the case of Fe the contamination level was $\textrm{10}^{13}$ atoms/$\textrm{cm}^2$ and showed similar results of above Cu cleaning. Fe was contaminated on Si surface by physical adsorption and as a particle type.

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PECVD와 고상결정화 방법을 이용한 poly-SiGe 박막의 제조

  • 이정근;이재진
    • Proceedings of the Korean Vacuum Society Conference
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    • 1998.02a
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    • pp.55.2-55
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    • 1998
  • 다견정 심리판-거l르마늄(JXlly-SiGe)은 TFT(thin-film transistor)와 갇븐 소자 응용에 있어서 중요한 불칠이다 .. LPCVD (low pressure chemical vapor deposition) 방법으로 비정칠 SiGc (a-SiGe) 박막올 증 착시키고 고상결정화(SPC: solid-phase crystallization)시켜 poly-SiGc옹 얻는 것은 잘 알려져 있다. 그러 나 그러나 PF'||'&'||'pound;VD-SPC 방법올 이용한 poly-SiGc의 제조에 대해서는 아직 두드러지게 연구된 바 없다. 우리단 PF'||'&'||'pound;VD 방법으로 a-SiGc 박막올 증착시키고 고상캘정화시켜 poly-SiGc올 얻었 R며, :~ 결정성, G Gc 농도, 결정핍의 평끌 크기 눔올 XRD (x-ray diffraction) 방법으호 조사하였다. 특히 pr'||'&'||'pound;VD 증착시 가판온도,Gc 함유량 등이 고상화에 미치는 영향에 대해서 조사하였다. P PECVD 장치는 터보펌프콸 사용하여 71저진공이 2xlOlongleftarrow5 Torr에 이르렀다. 가판윤 SiOOO) 웨이퍼륜 사용하고 기판 온도는 약 150- 35()"C 사이에서 변화되었다. 증착가스는 SiH4, GcH4, 112 등흘 썼다. 증착 압력과 r.f 전력용 각각 O.25ToIT와 3W로 일정하게 하였다 .. Gc 함유량(x)은 x x=O.O-O.5 사이에서 변화되었다 .. PECVD모 증착된 SiGc 박막들은 고상결정화를 위해 $\theta$X)"(:: Nz 분위기에서 24시간동안, 혹은 5OO'C에서 4열간 가열되었다. 고상결정화 후 poly-SiGc 박막은 SiGc(Ill), (220), (311) XRD 피크들올 보여주었으며, 각 피 크들은 poly-Si에 비하여 왼쪽으로 Bragg 각이 이동되었고, Vegard’slaw에 의해서 x의 값올 확 인할 수 있었다. 이것온 RBS 결과와 열치하였다. 약 150-350'C 사이에서 변화된 기판온도의 범위 에서 증착온도가 낮올수콕 견정립의 크기는 대체로 증가하는 것으로 나타났다 .. XHD로 추정된 형 균 결정립의 크기는 최대 약 3$\alpha$1m 정도였다. 또한 같끈 샘플뜰에 대해서 기판온도가 낮올수록 증착속도가 증가함옴 확인하였다 .. Gc 함유량이 x=O.1에서 x=O.5로 증가함에 따라서도 결정립의 크기와 SiGc 증착속도는 증가하는 것으로 나타났다 .. Hwang [1] , Kim[2] 둥의 연구자들은 Gc 함유 량이 증가함에 따라 결정 립 크기가 캄소하는 것올 보고하였으냐, Tsai [3] 둥은 반대의 결과플 보 고하고 Ge 힘유량의 증가시 결정립 크기의 증가에 대해 Gc의 Si보다 낮은 융점 (melting point) 올 강조한 바 있다. 결정립 크기의 증가는 대체로 SiGe 중착속도의 증가와도 관련이 있음올 볼 때, poly-SiGc의 경우에도 polv-Si의 고상화에서와 같이 증착속도가 빠를수록 최종적언 결정럽의 크기가 커지는 것으로 이해될 수도 있다 .. PECVD 증착시 증착속도의 증가는 증착된 박딱에서의 무켈서도를 증 가시킬 수 있음올 고려하면, 이라한 결파플온 p이y-SiGc의 고상결정화에서도 ploy-Si의 고상결정 화에서와 마찬가지로 초기 박막에서의 구조직 무절서도가 클수록, 고상결정화 후 결정 립의 크기 가 커칠 수 있음올 보여준다고 생각휠 수 있다,

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Post annealing effect on the photoluminescence properties of ZnO thin films prepared by atomic layer epitaxy (Atomic Layer Epitaxy에 의해 제작된 ZnO 박막의 후열처리에 따른 발광특성 연구)

  • 신경철;임종민;강승모;이종무
    • Journal of the Korean Vacuum Society
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    • v.13 no.3
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    • pp.103-108
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    • 2004
  • High-quality ZnO films were grown on sapphire (001) substrates by the atomic layer epitaxy (ALE) technique using DEZn as a Zinc precusor and $H_2O $ as an oxidant at both $170^{\circ}C$ and $400^{\circ}C$ which are in the ALE and the CVD process temperature ranges, respectively. The films were annealed in an oxygen atmosphere in the temperature range from 600 to 100$0^{\circ}C$ for an hour and then investigate photoluminescence (PL) properties using He-Cd laser. PL intensity tends to increases as the annealing temperature increase for both the annealed ZnO films grown at $170^{\circ}C$ and $400^{\circ}C$ , while PL did not nearly occur at the as-deposited ones. The PL intensity of the ZnO film grown at $400^{\circ}C$ is low after it is annealed at high temperature owing to a large number of Zn-Zn bonds although it has increased in the visible light wavelength region after annealing. In contrast the PL intensity has increased significant in the visible light region after annealing

Electrical Characteristics of PECVD $Ta_2O_5$ Dielectic Thin Films on HSG and Rugged Polysilicon Electrodes (입체표면 폴리실리콘 전극에서 PECVD $Ta_2O_5$ 유전박막의 전기적 특성)

  • Cho, Yong-Beom;Lee, Kyung-Woo;Chun, Hui-Gon;Cho, Tong-Yul;Kim, Sun-Oo;Kim, Hyeong-Joon;Koo, Kyung-Wan;Kim, Dong-Won
    • Journal of the Korean Vacuum Society
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    • v.2 no.2
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    • pp.246-254
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    • 1993
  • In order to increase the capacitance of storage electrode in the DRAM capacitor, two approaches were performed. First, hemispherical and rugged poly silicon films were made by LPCVD to increase the effective surface area of storage electrode. The even surface morphology of conventional poly silicon electrode was changed into the uneven surface of hemispherical of rugged poly silicon films. Second, PECVD $Ta_2O_5$ dielectric films were deposited and thermally treated to study the dielectrical characteristics of $Ta_2O_5$ film on each electrode. MIS capacitors with $Ta_2O_5$ films were electrically characterized by I-V, C-V and TDDB measurements. As a result, the capacitance of the electrode with uneven surface were increased by a factor of 1.2~1.5 and leakage current was increased compared with those of even surface. TDDB result indicates that the electrode with uneven surface has dielectrically more degraded than that of even surface. These results can be helpful as a basic research to develop new generation DRAM capacitors with $Ta_2O_5$ films.

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