• Proceedings of the KIEE Conference
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• 2006.04b
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• pp.244-246
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• 2006

This paper deals with an analysis of SCR thyristor switching pattern for a power quality disturbance generator with phase jump function. The proposed generator can be applied to the performance test of custom power devices. Voltage sag, swell, outage, unbalance and phase jump after outage are provided by the generator. The phase jump operating principle of the generator is described and analysed. Especially, a proper switching of the SCR thyristors for the proposed generator is important to guarantee the system reliability. Therefore the switching patterns for the thyristors in each made were analysed.

• Proceedings of the KIEE Conference
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• 2004.05a
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• pp.153-155
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• 2004

In this paper, we design the memory tester chip playing an important role in the memory tester as central parts. Memory tester has the sixteen inner instructions to control the test sequence and the address and data signals to DUT. These instructions are saved in memory with each block such as sequencer and pattern generator. Sequencer controls the test sequence according to instructions saved in the memory. And Pattern generator generates the address and data signals according to instructions saved in the memory, too. We can use these chips for various functional test of memory.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.292-301
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• 2001

IDDQ Testing is a very effective testing method to detect many kinds of physical defects occurred in CMOS VLSI circuits. In this paper, we consider the most commonly occurring bridging faults in current CMOS technologies and develop pattern generator for IDDQ testing using efficient IDDQ test algorithms. The complete set of bridging faults between every pair of all nodes(internal and external nodes) within circuit under test is assumed as target fault model. The merit of considering the complete bridging fault set is that layout information is not necessary. Implemented test pattern generator uses a new neighbor searching algorithm and fault collapsing schemes to achieve fast run time, high fault coverage, and compact test sets. Experimental results for ISCAS benchmark circuits demonstrate higher efficiency than those of previous methods.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.51 no.1
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• pp.23-28
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• 2002

In order to survey the radiation characteristics of pure line noise of unwanted noise from overhead high voltage AC transmission lines, a disk type gap noise generator was manufactured. Disk size which decides capacitance between the noise generator and earth was selected through preliminary indoor experiments and analysis by using surface charge method. The capacitance is one of principal parameters related to the injection of a proper noise current into lines. On the basis of the capacitance obtained from calculation, 5mm of space was given to the gap of the noise generator to be installed o test line and an aluminum disk of 60cm radius was made. The field experiments were performed with the noise generator hung on the Kochang 765 kV full scale test line. As the results, the useful data which can be used to analysis the radiation characteristics of noise from transmission lines were obtained. Those are the directivity of antenna toward the line, lateral profiles, frequency spectra, height pattern and so on.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.6
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• pp.1138-1143
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• 2011

One of the critical items in radar testing is the ability to evaluate the performance of radar systems under real operational environments. But it takes lots of time and cost to operate real targets and analyze the test results due to a large amount of data based on these complicated environments. In this paper, the Radar Simulative T&E Lab. is introduced, and the test and analysis results of the developing radar for predicting the radar system performance are described in the Radar Simulative T&E Lab. This laboratory could be used to test the far-field characteristics of antenna radiation pattern and to perform an effective radar system test and evaluation using a simulative target generator under a low cost repeating test situation.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.16 no.6
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• pp.62-70
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• 2007

In this study, the natural flaws in welding parts are classified using the signal pattern classification method. The storage digital oscilloscope including FFT function and enveloped waveform generator is used and the signal pattern recognition procedure is made up the digital signal processing, feature extraction, feature selection and classifier design. It is composed with and discussed using the distance classifier that is based on euclidean distance the empirical Bayesian classifier. Feature extraction is performed using the class-mean scatter criteria. The signal pattern classification method is applied to the signal pattern recognition of natural flaws.

• Proceedings of the KIEE Conference
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• 1998.07e
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• pp.1721-1724
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• 1998

A shorted-turn test was performed at the Pyungtaek combined cycle power plant on gas. turbine generator #4. The test was conducted using a permanent flux probe and digital oscilloscope. The flux probe installed in the generator air gap, senses the field winding slot leakage flux and produces a voltage proportional to the rate of change of the flux. This pattern of flux variation is a signature unique to each field winding. We have also applied a waveform analysis technique that can identify the pole location, slot number, and number of shorted-Turns with each slot.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.229-240
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• 1995

This paper proposes a new weighted random pattern testing technique to detect path delay faults in combinational logic circuits. When computing the probability of signal transition at primitive logic elements of CUT(Circuit Under Test) by the primary input, the proposed technique uses the information on the structure of CUT for initialization vectors and vectors generated by pseudo random pattern generator for test vectors. We can sensitize many paths by allocating a weight value on signal lines considering the difference of the levels of logic elements. We show that the proposed technique outperforms existing testing method in terms of test length and fault coverage using ISCAS '85 benchmark circuits. We also show that the proposed testing technique generates more robust test vectors for the longest and near-longest paths.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.33-40
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• 2008

As the speed of memory is improved vey fast the advanced test equipments are needed to test the ultra-high speed memory devices efficiently. It is necessary to develop the Algorithmic Pattern Generator (ALPG) that tests fast memory devices effectively using the instructions that testers want to use. In this paper, we propose a new parallel ALPG for the ultra-high speed memory testing. The proposed ALPG can generate patterns for fast memory devices at high speed using manual instructions by the Instruction Analyzer.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1968-1971
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• 2002

In this paper, we have presented a test- ing method for a kind of asynchronous circuits. Tar- get circuit model is the 3D machine that is one of the most successful implementation of extended burst-mode (XBM) machines. We present a high-level test generation method for the 3D machine using the specification of the circuit. We also present a gate-level test pattern generation method using a synchronous test pattern generator. Experimental results show that the combination of the above two methods achieves high fault coverage over 3D machines and saves test generation time.