• Journal of International Academy of Physical Therapy Research
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• v.3 no.1
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• pp.370-377
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• 2012

This study examines the effects of different environments on the application of hemiplegia patients circuit balance training. Group 1 performed circuit balance training without any auditory intervention Group 2 performed training in noiseless environments and Group 3 performed training in white noise environments. First, among lower extremity muscular strength evaluation items, maximum activity time(MAT) was not significantly different(p>.05). Maximum muscle strength(MMS) increased significantly in Group 3(p<.01), there was no significant difference in MMS among the groups. Average muscle strength(AMS) indexes also significantly increased in Group 3(p<.01), there was no significant difference in AMS among the groups. Second, among balancing ability evaluation items, Berg's balance scale(BBS) scores significantly increased in all groups(p<.05), BBS scores were significantly difference among the groups. Based on the results, Group 1, 2 and Group 1, 3 showed significant increases (p<.05). Functional reach test(FRT) values significantly increased in Group 2, 3(p<.05), and there was no significant difference in FRT values among the groups. Timed up and go(TUG) test values significantly decreased in Group 2, 3(p<.05), and there was no significant difference in TUG test values among the groups. Third, among walking speed evaluation items, the time required to walk 10m significantly decreased in all groups(p<.05), and there was no significant difference in the values among the groups. Average walking speeds showed significant increases in Group 1, 3(p<.05), and there was no significant difference in the values among the groups. Based on the results of this study, noise environments should be improved by either considering auditory interventions and noiseless environments, or by ensuring that white noise environments facilitate the enhancement of balancing ability.

• Journal of Radiation Protection and Research
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• v.25 no.4
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• pp.197-205
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• 2000

A prototype electronic dosimeter(PED) adopting a silicon PIN diode detector as a radiation detector has been developed, manufactured and test-evaluated. A radiation signal processing circuit has been electronically tested and then the radiation detection characteristics of this PED has been performance-tested by using a reference photon radiation field. As a result in a electronic performance test, radiation signals from a detector were well observed in the signal processing circuit. The radiation detection sensitivity of this PED after several test-irradiations to $^{137}Cs$ gamma radiation source appeared to be 1.85 cps/$Gy{\cdot}h^{-1}$ with 19.3% of the coefficient of variation, which satisfied the performance criteria for the active personnel radiation monitor. Further improvement of the electronic circuit and operating program will enable the PED to be used in personal monitoring purpose.

• Journal of Digital Contents Society
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• v.18 no.3
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• pp.607-612
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• 2017

The use of RaspberryPi in building an embedded system may be difficult for users in understanding the circuit and the hardware cost. This paper proposes a solution that can test the systems virtually. The solution consists of three elements; (i) editor, (ii) interpreter and (iii) simulator and provides nine full modules and also allows the users to configure/run/test their own circuits like real environment. The task of abstraction for modules through the actual circuit test was carried out on the basis of the data sheet and the specification provided by the manufacturer. If we can improve the level of quality of our solution, it can be useful in terms of cost reduction and easy learning. To achieve this end, the electrical physics engine, the level of interpreter that can be ported to the actual board, and a generalization of the simulation logic are required.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09a
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• pp.154-157
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• 2003

In order for testing faults of combinatorial logic circuit, the authors have developed a new diagnosis method: "Neural Network (NN) fault diagnosis", based on fm error back propagation functions. This method has proved the capability to test gate faults of wider range including so called SSA (single stuck-at) faults, without assuming neither any set of test data nor diagnosis dictionaries. In this paper, it is further shown that what kind of fault models can be detected in the NN fault diagnosis, and the simply modified one can extend to test delay faults, e.g. logic hazard as long as the delays are confined to those due to gates, not to signal lines.

• Progress in Superconductivity
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• v.11 no.1
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• pp.19-24
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• 2009

Among the various types of fault current limiters, superconducting fault current limiters could be the most preferable choice for high voltage electric power systems owing to the remarkable current limiting characteristics of superconductors. But, there have been no commercial superconducting fault current limiters which were installed into actual electric power systems until these days due to some remained technical and economical problems. Thus, in order to promote the development and application of the superconducting fault current limiters into real field, it is essential to understand the power utilities’ requirements for their networks and also suitable test method and some specifications should be prepared. This paper focuses on the matters of test requirements and standardization issues that should be prepared for commercialization of superconducting fault current limiters. The unique current limiting characteristics of superconducting fault current limiters were investigated and related other standards including circuit breakers, transformers, reactors, power fuse, and fused circuit breakers were compared to setup the basis of novel specification of superconducting fault current limiters. Furthermore, required essential test procedures for superconducting fault current limiters were suggested.

• Proceedings of the KIEE Conference
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• 2008.11a
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• pp.150-152
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• 2008

It is necessary to improve the time efficiency in the high power testing station because tests are mainly performed by high-priced equipment. Minimizing a human error through building the database of relevant standards is possible to expect reliable tests. And also, application program that is properly customized for the certain laboratory's power system will help test engineer to easily analyze the phenomenon that is happened in short-circuit and load switching tests. This paper introduces the several functions of the application program that is developed in order to realize these requirements.

• Journal of Electrical Engineering and Technology
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• v.3 no.1
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• pp.130-134
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• 2008

The increasing size of very large scale integration (VLSI) circuits, high transistor density, and popularity of low-power circuit and system design are making the minimization of power dissipation an important issue in VLSI design. Test Power dissipation is exceedingly high in scan based environments wherein scan chain transitions during the shift of test data further reflect into significant levels of circuit switching unnecessarily. Scan chain or cell modification lead to reduced dissipations of power. The ETC algorithm of previous work has weak points. Taking all of this into account, we therefore propose a new algorithm. Its name is RE_ETC. The proposed modifications in the scan chain consist of Exclusive-OR gate insertion and scan cell reordering, leading to significant power reductions with absolutely no area or performance penalty whatsoever. Experimental results confirm the considerable reductions in scan chain transitions. We show that modified scan cell has the improvement of test efficiency and power dissipations.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.38-40
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• 2001

Measuring technology based on the computer and software is used worldwideiy by the aids of remarkably improved digital technology and measuring devices, and the electro- magnetic interference due to high currents and high voltages is being solved by the helps of applied optic instrumentation technology. The automatic acquisition, analysis and storage system of test data is available for utilizing the numerical computation technology. The measuring accuracy and testing efficiency are thus much higher because of the developed technologies. In this paper, the construction of data acquisition system in KERI including measuring devices and its application to the short circuit test are described, and additionally the algorithm of the analyzing program for the automatic process of test data and the results of analyses are described.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.9
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• pp.1442-1447
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• 1990

In this paper we propose the search algorithm of the boundary nodes that defined as the circuit segmentation when CUT is tested by pseudo-exhaustive testing. The algorithm treats the testability values of the nodes in CUT as the population composed of teh raw data, and after examines the level of significance a and then estimate the confidence interval of teh testability values. Thus One can easily searched the c9oundary nodes and PO of sub circuits. The proposed algorithm has been implemented under UNIX OS with C-language, applied to the combinational logic CUT. As a result, it is shown that the pseudo-exhaustive test patterns are least generated when \ulcornerhas 0.786. We confirmed that the rate of test pattern is 1.22%, compared with exhaustive test.

• Corrosion Science and Technology
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• v.7 no.1
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• pp.61-67
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• 2008

In this paper, electrochemical and microstructural characteristics of nickel-plated Alloy 600 were investigated in order to identify the performance of electroless Ni-plating on Alloy 600 in high-temperature aqueous condition with the comparison of electrolytic nickel-plating. For high temperature corrosion test of nickel-plated Alloy 600, specimens were exposed for 770 hours to typical PWR primary water condition. During the test, open circuit potentials (OCP's) of all specimens were measured using a reference electrode. Also, resistance to flow accelerated corrosion (FAC) test was examined in order to check the durability of plated layers in high-velocity flow environment at high temperature. After exposures to high flow rate aqueous condition, the integrity of surfaces was confirmed by using both scanning electron microscopy (SEM) and energy dispersive spectroscopy (EDS). For the field application, a remote process for electroless nickel-plating was demonstrated using a plate specimen with narrow gap on a laboratory scale. Finally, a practical seal design was suggested for more convenient application.