• Title/Summary/Keyword: test circuit

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Compact Range Detection Sensor by Oscillation Frequency Deviation of an Active Antenna (능동안테나의 발진주파수 편이에 의한 소형 거리 센서)

  • Yun, Gi-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.3
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    • pp.528-535
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    • 2011
  • In this paper, a compact doppler sensor with oscillator type active antenna operating at 2.4GHz frequency band is proposed to measure the distance to a moving object. The oscillation frequency is shifted depending on approaching of the object, and a detection circuit discriminates the frequency deviation. The active antenna has been designed and simulated. The prototype fabricated has a small circular disk type of diameter 30mm and height 4.2mm. As for antenna performance, broadside radiation pattern with beamwidth of $120^{\circ}$ and oscillation frequency of 2.35GHz has been measured. Test results as a range sensor shows that signal voltage of about 240mV has been obtained for conducting plate moving 1 meter away from the sensor. And, signal voltage has been linearly increased to the ground from 5m height by free-falling the sensor.

SoC Design for Malicious Circuit Attack Detection Using on-Chip Bus (온칩버스를 이용한 악성 회로 공격 탐지 SoC 설계)

  • Guard, Kanda;Ryoo, Kwang-ki
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.10a
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    • pp.885-888
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    • 2015
  • A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connect (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 40K at an operating frequency of 250MHz using the $0.13{\mu}m$ TSMC process.

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Development of Transportational Guide System for Joining Small Wire with Gabion (개비온 끝단 소둔선 결합용 이송 가이드 장치 개발 연구)

  • Lee, Jong kil;Kin, Jong-Tae
    • 대한공업교육학회지
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    • v.31 no.1
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    • pp.211-225
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    • 2006
  • Gabion can be used for the purpose of preventing overflow of river and side loss of road. However the manufacturing process of the gabion is manually controlled especially to the joining process at the terminal part of gabion with small diameter wire. In this paper automatic feeding guide system was designed and fabricated to make automation. The fabricated system was tested in the factory level. Pneumatic system was considered as the main idea of the feeding system. 3/2-way and 5/2-way manual control valve, eight double-acting cylinders were used. The system took 46.48 seconds during a cycle. Additional environmental noise and vibration were not detected when the machine operated at the working area. Based on the theoretical simulation and actual test the fabricated system was well controlled. The system was applied to the patent in 2006.

Boost Converter Embedded Battery Charging Function for Application of E-bike (전기자전거 응용을 위한 배터리 충전 기능 내장형 부스트 컨버터)

  • Kim, Da-Som;Kim, Sang-Yeon;Kang, Kyung-Soo;Roh, Chung-Wook
    • The Transactions of the Korean Institute of Power Electronics
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    • v.21 no.2
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    • pp.175-181
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    • 2016
  • In the conventional E-bike, a 42 V/10 A Li-ion battery drives a 24 V/10 A BLDC motor via a 6-switch PWM DC/AC inverter. The major problems of the conventional battery-fed motor drive systems are listed as follows. To charge the battery, an external battery charger (adapter) is required, which degrades the portability of E-bike users. In addition, given the high-frequency operation of the motor drive inverter, the switching losses are significant, which degrades the whole power efficiency. High-voltage batteries (42 V) require a complex battery management system (BMS), which degrades the reliability of the battery pack. In this paper, an embedded boost-converter battery charger for E-bikes is proposed. The variable output boost converter, which converts 16.8 V battery voltage to the required variable voltage of the inverter input, can use a low-voltage battery and thus improve the reliability of batteries. By varying the inverter input voltage via boost converter, a DC link voltage control method can be applied to reduce the switching frequency of the inverter, which improves the whole power efficiency. Given that the function of a flyback charger is integrated in the proposed boost converter, the portability of the E-bike user can be maximized by excluding an external adapter. The validity of the proposed circuit will be confirmed by operation mode analysis and simulation. Moreover, experimental results of integrative charger using Li-ion battery and 200 W motor test will be showed with a prototype sample as well.

Bidirectional Charging/Discharging Digital Control System for Eco-friendly Capacitor Energy Storage Device Implemented by TMS320F28335 chip (TMS320F28335로 구현한 친환경 커패시터 전력저장장치의 양방향 디지털 제어 충/방전 시스템)

  • Lee, Jung-Im;Lee, Jong-Hyun;Jung, An-Yoel;Lee, Choon-Ho;Park, Joung-Hu;Jeon, Hee-Jong
    • The Transactions of the Korean Institute of Power Electronics
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    • v.15 no.3
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    • pp.188-198
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    • 2010
  • Recently, as the demand of the environmental-friendly energy storage system such as an electric double-layer condenser increases, that of the bidirectional charger/discharger for the systems also increases. However, when charging/discharging mode-change occurs, the charger/discharger employing a bi-directional DC-DC converter with a commercialized analog controller has a complex circuit scheme, and a poor transient response. On the other hand, if a single digital controller is used for the bi-directional mode, the system performances can be improved by application of an advanced power-processing algorithm. In the paper, an environmental-friendly power storage systems including an Electric Double Layer Capacitor(EDLC) banks were developed with a bi-directional buck-boost converter and a digital signal processor (TMS320F28335). A simulation test-bed was realized and tested by MATLAB Simulink, and the hardware experiment was performed which shows that the dynamic response was improved such as the simulation results.

Development of Recycled Aggregate Producing Circuit Using Autogenous mill (Autogenous mill을 이용(利用)한 순환골재(順換骨材) 생산(生産) 공정(工程) 개발(開發))

  • Kim, Kwan-Ho;Lee, Duck-Jae;Cho, Hee-Chan;Ahn, Ji-Whan
    • Resources Recycling
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    • v.16 no.5
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    • pp.25-30
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    • 2007
  • In Korea, reutilization of construction waste is gaining attention as construction waste generated increases continuously. Currently, the concrete waste is simply crushed and used as a low value application such as paving, back filling, etc. To meet the demand of aggregate for construction and the resource efficiently, production of high quality recycled aggregate is necessary. Therefore, in this study, a better process for production of high quality recycled aggregate was developed using combination of heat pretreatment and autogenous milling. Test results showed that the recycled aggregate has a density of $2.5\;g/cm^3$ and a water absorption ratio of 3.0%, which meet the specification of the first class of KS F 2573. Currently, a pilot scale autogenous mill is being constructed and tests will be further conducted to develop a commerce-scale process.

Module Design and Performance Evaluation of Surge Arrester for Loading In Railway Rolling Stock (전철 탑재형 피뢰기의 모듈설계 및 성능평가기술)

  • Cho, H.G.;Kim, S.S.;Han, S.W.;Lee, U.Y.
    • Proceedings of the KIEE Conference
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    • 2000.07c
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    • pp.2038-2040
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    • 2000
  • The main objective of this paper is to design and test a new type of polymer ZnO surge arrester for AC power system of railroad vehicles. Metal oxide surge arrester for most electric power system applications, electric train and subway are now being used extensively to protect overvoltage due to lightning. Surge arresters with porcelain housing must not have explosive breakage of the housing to minimize damage to other equipment when subjected to internal high short circuit current. When breakdown of ZnO elements in a surge arrester occurs due to flashover, fault short current flows through the arrestor and internal pressure of the arrester rises. The pressure rise can usually be limited by fitting a pressure relief diaphragm and transferring the arc from the inside to the outside of the housing. However, there is possibility of porcelain fragmentation caused by the thermal shock, pressure rise. etc. Non-fragmenting of the housing is the most desired way to prevent damage to other equipment. The pressure change which is occurred by flashover become discharge energy. This discharge energy raises to damage arrester housing and arrester housing is dispersed as small fragment. Therefore, the pressure relief design is requested to obstruct housing dispersion. The main research works are focused on the structure design by finite element method, pressure relief of module, and studies of performance of surge arrester for electric railway vehicle.

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The Design of Multi-channel Synchronous Communication IC Using FPGA (FPGA를 이용한 다채널 동기 통신용 IC 설계)

  • Yang, Oh;Ock, Seung-Kyu
    • Journal of the Semiconductor & Display Technology
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    • v.10 no.3
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    • pp.1-6
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    • 2011
  • In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

Design of a 2.5GHz Quadrature LC VCO with an I/Q Mismatch Compensator (I/Q 오차 보정 회로를 갖는 2.5GHz Quadrature LC VCO 설계)

  • Byun, Sang-Jin;Shim, Jae-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.2
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    • pp.35-43
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    • 2011
  • In this paper, an analysis on I/Q mismatch characteristics of a quadrature LC VCO(Voltage controlled oscillator) is presented. Based on this analysis, a new I/Q mismatch compensator is proposed. The proposed I/Q mismatch compensator utilizes an amplitude mismatch detector rather than the conventional phase mismatch detector requiring much more wide frequency bandwidth. To verify the proposed circuit, a 2.5GHz quadrature LC VCO was designed in a $0.18{\mu}m$ CMOS process and tested. Test results show that an amplitude mismatch detector achieves similar I/Q mismatch compensation performance as that of the conventional phase mismatch detector. The I/Q mismatch compensator consumes 0.4mA from 1.8V supply voltage and occupies $0.04mm^2$.

Altered Peripheral Nerve Excitability Properties in Acute and Subacute Supratentorial Ischemic Stroke (급성 및 아급성 천막상 허혈성 뇌졸중에서 발생하는 말초신경 흥분성 변화)

  • Seo, Jung Hwa;Ji, Ki Whan;Chung, Eun Joo;Kim, Sang Gin;Kim, Oeung Kyu;Paeing, Sung Hwa;Bae, Jong Seok
    • Annals of Clinical Neurophysiology
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    • v.14 no.2
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    • pp.64-71
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    • 2012
  • Background: It is generally accepted that upper motor neuron (UMN) lesion can alter lower motor neuron (LMN) function by the plasticity of neural circuit. However there have been only few researches regarding the axonal excitability of LMN after UMN injury especially during the acute stage. The aim of this study was to investigate the nerve excitability properties of the LMNs following an acute to subacute supratentorial corticospinal tract lesion. Methods: An automated nerve excitability test (NET) using the threshold tracking technique was utilized to measure multiple excitability indices in median motor axons of 15 stroke patients and 20 controls. Testing of both paretic and non-paretic side was repeated twice, during the acute stage and subacute stage. The protocols calculated the strength-duration time constant from the duration-charge curve, parameters of threshold electrotonus (TE), the current-threshold relationship from sequential sub-threshold current, and the recovery cycle from sequential supra-threshold stimulation. Results: On the paretic side, compared with the control group, significant decline of superexcitablity and increase in the relative refractory period were observed during the subacute stage of stroke. Additionally, despite the absence of statistical significance, a mildly collapsing in ('fanning in') of the TE was found. Conclusions: Our results suggest that supratentorial brain lesions can affect peripheral axonal excitability even during the early stage. The NET pattern probably suggests background membrane depolarization of LMNs. These features could be associated with trans-synaptic regulation of UMNs to LMNs as one of the "neural plasticity" mechanisms in acute brain injury.