• 전자공학회논문지A
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• 제33A권10호
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• pp.152-159
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• 1996

We have designed and implemented an optoelectronic hardware of binary phase extraction joint transform correlator (BPEJTC) which provides higher peak-to-sidelobe ratio than many other versions of JTC that has been published so far and does not produce correlation peaks due to intra-class association, to construct a multi-target tracking system. The digital processing unit controlling the entire system plays the part of modifying and binarizing the joint transform power spectrum (JTPS) and the optical processing unit is mainly used to take fourier transform operations. Some experimental results conducted by designed system along with its architecture showed the processing rate of 6 frames per second, thereby the potential applicability of the proposed system to real-time multitarget tracking system is given.

• 대한전자공학회논문지
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• 제16권6호
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• pp.40-47
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• 1979

PCM의 기본단말인 신형 D-4 channel bank의 개발에 있어서 alarm과 trunk pocessing unit에 마이크로프로세서를 활용하여 많은 기능을 부가하였고 이로 인해 회로소자의 간소화와 높은 신뢰성을 얻게 되었다. LSI기술을 지향하는 선진국에 반하여, 아직 국내 반도체산업의 후진을 면치 못하는 우리 나라의 경우 산업용 시스템에 마이크로프로세서의 응용은 경제성, 신뢰성, 기술성에서 높은 의의를 준다.

• 전자공학회논문지B
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• 제30B권5호
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• pp.73-81
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• 1993

We have developed a system which can analyze the status of signal sent from/received to a signalling service equipment within the fully electronic switching system such as TDX-10. The system has such functions that acquire PCM signal of the preferred channel from the subhighway of the thirth-two channel by which a Universal Signal Tr ansceiver Unit(USTU) is connected with Time Switch Unit (TSU), and then classify the type of signal such as R2MFC/DTMF/CCT/VOICE, and determine the digit. Up to now, we have analyzed the frequency spec trum using the FFT. This paper describes the developement of PCM acquirer which can analyze the signal characteristics by acquiring the PCM signal in SHW(subhighway), and proposes the CZT(Chirp Z-Transform) algorithm. An algorithm which analyzes the acquired signal and determines the signal frequency and the corresponding power spectrum using the CZT is also discussed here.

• 전자공학회논문지D
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• 제34D권7호
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• pp.88-96
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• 1997

As the need of automatized system has been increased recently together with the development of industrial and military technologies, the adaptive real-time target detection technologies that can be embedded on vehicles, planes, ships, robots and so on, are hgihly demanded. Accordingly, this paper proposes a novel approach to detect and segment the moving targets using the binary phase extraction joint transform correlator (BPEJTC), the advanced image subtraction filter and convex hull processing. The BPEJTC which was used as a target detection unit mainly for target tracking compensating the camera movement. The target region has been detected by processing the successful three frames using the advanced image subtraction filter, and has become more accurate by applying the developed convex hull filter. As shown by some experimental results, it is expected that the proposed approaches for compensation of the camera movement and segmentationof of target region, can be used for th emissile guiddance, aero surveillance, automatic inspectin system as well as the target detection unit of automatic target recognition system that request adaptive real-time processing.

• 대한전자공학회논문지
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• 제27권7호
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• pp.1015-1024
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• 1990

This paper proposes a program counter unit(PCU) on the pipelined architecture of RISC (Reduced Instruction Set Computer) type high performance processors, PCU is used for supplying instruction addresses to memory units(Instruction Cache) efficiently. A RISC processor's PCU has to compute the instruction address within required intervals continnously. So, using the method of self-generated incrementor, is more efficient than the conventional one's using ALU or private adder. The proposed PCU is designed to have the fast +4(Byte Address) operation incrementor that has no carry propagation delay. Design specifications are taken by analyzing the whole data path operation of target processor's default and exceptional mode instructions. CMOS and wired logic circuit technologic are used in PCU for the fast operation which has small layout area and power dissipation. The schematic capture and logic, timing simulation of proposed PCU are performed on Apollo W/S using Mentor Graphics CAD tooks.

• 전자공학회논문지B
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• 제28B권10호
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• pp.747-754
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• 1991

In this paper, we studies the on-line recognition of handwritten character using WLD(weighted levenshtein distance) algorithm with parallelism. The Hangeul can be separated for unit of phonemes and the alphanumeric can be separated for unit of characters. And, we studies the parallelism and the concurrency of the WLD algorithm for realization of special-purpose processor. By the simulation result for 10, 000 characters in practical sentences, the recognition rate of strokes in obtained 96.57$\%$ and the separation rate for phonemes and characteristics is obtained 95.4$\%$.

• 전자공학회논문지C
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• 제34C권6호
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• pp.22-27
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• 1997

This paper propose a novel VLSI architecture for a multiplierless FIR filter chip providing variable-length taps. To change the number of taps, we propose two special features called a data-reuse structure and a recurrent-coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and a modulo unit. Since multipliers occupy large VLSI area, a multiplierless filter chip meeting real-time requirement can save large area. We propose a modified bit-serial multiplication algorithm to compute two partial products in parallel, and thus, the proposed filter is twice faster and has smaller hardware than previous multiplierless filters. We developed VHDL models and performed logic synthesis using the 0.8.mu.m SOG (sea-of-gate) cell library. The chip has only 9,507 gates, was fabricated, and is running at 77MHz.

• 대한전자공학회논문지
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• 제23권3호
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• pp.327-339
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• 1986

In this paper, a hardware compiler for symbolic description language(SDL) is proposed for logic design automation. Lexical analysis is performed for SDL which describes the behavioral characteristics of a digital system at the register transfer level by the proposed algorithm I. The algorithm I is proposed to get the expressions for the control unit and for the data transfer unit. In order to obtain the network description language(NDL) expressions equivalent to gate-level logic circuits, another algorithm, the the algorithm II, is proposed. Syntax analysis for the data formed by the algorithm I is also Performed using circuit elements such as D Flip-Flop, 2-input AND, OR, and NOT gates. This SDL hardware compiler is implemented in the programming language C(VAX-11/750(UNIX)), and its efficiency is shown by experiments with logic design examples.

• 대한전자공학회논문지
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• 제12권1호
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• pp.7-11
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• 1975

12-Tuple DS (digit sequence) (또는 coordinate sequence)의 여러 가지 성질에 관하여 논하였으며 그것을 통일적으로 표시하기 위한 31종의 PDS(prime digit sequence)를 제안하여 이에 단순히 회전변환만을 실시함으로써 실제의 부호를 표시하는 348종의 DS를 얻을 수 있고 또 이것들에 대한번호교환 즉 순열(permutation)과 부호의 초기조건을 고려하면 단위거리 12진 부호의 총수는 120,576종이며 이 중의 임의의 부호를 지정하든지 기술하든지 할 수 있도록 하였다. 그리고 대칭부호(반대부호), Lippel 부호등 특수한 부호를 위한 DS들의 특성과 그것들이 회로화에 대하여도 언급하였다. Investigations on sole characteristics of unit-distance duo-decimal codes are carried out, and 31kinds of Prime Digit Sequence (PDS) are proposed in order to express various digit sequences. From these PDS, by means of the rotational conversion, 348 digit sequences which express the practical GC are obtained, and, ism these digit sequences, it is found that there are 120576 unit distance codes by the permutation of the coordinate number and the initial condition of the codes. Some special codes such as reflected or symmetrical codes and Lippel codes, and their application to the practical GC counter are also studied.

• 대한전자공학회논문지
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• 제27권3호
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• pp.21-30
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• 1990

본 논문은 MC-CVQ(motion compensated and classified vector quantization) 알고리듬의 하드웨어 실현에 관한 것으로, $128{\times}128$화소로 구성된 흑백영상을 64Kbps채널로 1초에 약 10장의 화면을 전송할 수 있는 화면간 부호화장치의 제작에 대하여 설명하였다. 위의 조건하에서 보호화를 수행하기 위하여, 시스템을 MC부, CVQ부, 보호화부로 구분하여 마이크로프로그램 제어에 의한 멀티프로세서 구조로 구성하였다. 그리고 MC부와 CVQ부에서 최소 거리 오차를 효율적으로 계산하기 위하여 연산부에는 3~단 파이프라인 구조를 채택하였다. 시스템 제작 후 성능을 평가한 결과, 본 시스템의 화면전송율은 영상신호의 상대적 이동량에 따라 1초에 6~15장 정도임을 확인하였다.